FSConfig.py revision 5478
15323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 22934Sktlim@umich.edu# All rights reserved. 32934Sktlim@umich.edu# 42934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132934Sktlim@umich.edu# this software without specific prior written permission. 142934Sktlim@umich.edu# 152934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# Authors: Kevin Lim 282934Sktlim@umich.edu 292934Sktlim@umich.eduimport m5 302969Sktlim@umich.edufrom m5 import makeList 312934Sktlim@umich.edufrom m5.objects import * 322995Ssaidi@eecs.umich.edufrom Benchmarks import * 332934Sktlim@umich.edu 342934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 352934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 362934Sktlim@umich.edu read_only=False) 372934Sktlim@umich.edu 382934Sktlim@umich.edu def childImage(self, ci): 392934Sktlim@umich.edu self.image.child.image_file = ci 402934Sktlim@umich.edu 414520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 424520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 434982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 444520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 454520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 462934Sktlim@umich.edu 472934Sktlim@umich.edu self = LinuxAlphaSystem() 483005Sstever@eecs.umich.edu if not mdesc: 493005Sstever@eecs.umich.edu # generic system 503304Sstever@eecs.umich.edu mdesc = SysConfig() 512995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 522934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 532934Sktlim@umich.edu self.membus = Bus(bus_id=1) 544965Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 555266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 562934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 572934Sktlim@umich.edu self.bridge.side_b = self.membus.port 582934Sktlim@umich.edu self.physmem.port = self.membus.port 592934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 602934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 612995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 622934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 632934Sktlim@umich.edu self.tsunami = BaseTsunami() 642934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 652934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 662934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 672995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 682934Sktlim@umich.edu read_only = True)) 692934Sktlim@umich.edu self.intrctrl = IntrControl() 702953Sktlim@umich.edu self.mem_mode = mem_mode 715478Snate@binkert.org self.terminal = Terminal() 722934Sktlim@umich.edu self.kernel = binary('vmlinux') 733449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 742934Sktlim@umich.edu self.console = binary('console') 752934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 762934Sktlim@umich.edu 772934Sktlim@umich.edu return self 782934Sktlim@umich.edu 793584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 804486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 814486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 824486Sbinkertn@umich.edu read_only=False) 834486Sbinkertn@umich.edu 844486Sbinkertn@umich.edu def childImage(self, ci): 854486Sbinkertn@umich.edu self.image.child.image_file = ci 864486Sbinkertn@umich.edu 873584Ssaidi@eecs.umich.edu self = SparcSystem() 883584Ssaidi@eecs.umich.edu if not mdesc: 893584Ssaidi@eecs.umich.edu # generic system 903584Ssaidi@eecs.umich.edu mdesc = SysConfig() 913584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 923743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 933584Ssaidi@eecs.umich.edu self.membus = Bus(bus_id=1) 944972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 953743Sgblack@eecs.umich.edu self.t1000 = T1000() 964104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 973743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 983823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 993814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1003743Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1013743Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1023584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1033814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1043584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1053745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1063745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1073745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1083584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1093898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1103898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1113898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1124103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1134103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1144103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1153745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1163745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1173745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1183584Ssaidi@eecs.umich.edu 1193584Ssaidi@eecs.umich.edu return self 1203584Ssaidi@eecs.umich.edu 1215222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 1225222Sksewell@umich.edu class BaseMalta(Malta): 1235222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1245222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1255222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 1265222Sksewell@umich.edu 1275222Sksewell@umich.edu self = LinuxMipsSystem() 1285222Sksewell@umich.edu if not mdesc: 1295222Sksewell@umich.edu # generic system 1305222Sksewell@umich.edu mdesc = SysConfig() 1315222Sksewell@umich.edu self.readfile = mdesc.script() 1325222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 1335222Sksewell@umich.edu self.membus = Bus(bus_id=1) 1345222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1355222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1365222Sksewell@umich.edu self.bridge.side_a = self.iobus.port 1375222Sksewell@umich.edu self.bridge.side_b = self.membus.port 1385222Sksewell@umich.edu self.physmem.port = self.membus.port 1395222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1405222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1415222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 1425222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1435222Sksewell@umich.edu self.malta = BaseMalta() 1445222Sksewell@umich.edu self.malta.attachIO(self.iobus) 1455222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 1465222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 1475222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1485222Sksewell@umich.edu read_only = True)) 1495222Sksewell@umich.edu self.intrctrl = IntrControl() 1505222Sksewell@umich.edu self.mem_mode = mem_mode 1515478Snate@binkert.org self.terminal = Terminal() 1525222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 1535222Sksewell@umich.edu self.console = binary('mips/console') 1545222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1555222Sksewell@umich.edu 1565222Sksewell@umich.edu return self 1575222Sksewell@umich.edu 1585323Sgblack@eecs.umich.edudef x86IOAddress(port): 1595357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 1605323Sgblack@eecs.umich.edu return IO_address_space_base + port; 1615323Sgblack@eecs.umich.edu 1625299Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, mdesc = None): 1635299Sgblack@eecs.umich.edu self = LinuxX86System() 1645133Sgblack@eecs.umich.edu if not mdesc: 1655133Sgblack@eecs.umich.edu # generic system 1665133Sgblack@eecs.umich.edu mdesc = SysConfig() 1675133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 1685133Sgblack@eecs.umich.edu 1695133Sgblack@eecs.umich.edu # Physical memory 1705323Sgblack@eecs.umich.edu self.membus = Bus(bus_id=1) 1715450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1725133Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 1735133Sgblack@eecs.umich.edu 1745450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 1755450Sgblack@eecs.umich.edu # just to avoid corner cases. 1765450Sgblack@eecs.umich.edu assert(self.physmem.range.second >= 0x200000) 1775450Sgblack@eecs.umich.edu 1785450Sgblack@eecs.umich.edu # Mark the first megabyte of memory as reserved 1795450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 1805450Sgblack@eecs.umich.edu addr = 0, 1815450Sgblack@eecs.umich.edu size = '1MB', 1825450Sgblack@eecs.umich.edu range_type = 2)) 1835450Sgblack@eecs.umich.edu 1845450Sgblack@eecs.umich.edu # Mark the rest as available 1855450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 1865450Sgblack@eecs.umich.edu addr = 0x100000, 1875450Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 - 1), 1885450Sgblack@eecs.umich.edu range_type = 1)) 1895450Sgblack@eecs.umich.edu 1905323Sgblack@eecs.umich.edu # North Bridge 1915323Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1925323Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1935323Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1945323Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1955323Sgblack@eecs.umich.edu 1965330Sgblack@eecs.umich.edu # Command line 1975416Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=9608015' 1985330Sgblack@eecs.umich.edu 1995133Sgblack@eecs.umich.edu # Platform 2005389Sgblack@eecs.umich.edu self.pc = PC() 2015389Sgblack@eecs.umich.edu self.pc.attachIO(self.iobus) 2025133Sgblack@eecs.umich.edu 2035133Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 2045133Sgblack@eecs.umich.edu 2055133Sgblack@eecs.umich.edu return self 2065133Sgblack@eecs.umich.edu 2073584Ssaidi@eecs.umich.edu 2083025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 2092934Sktlim@umich.edu self = Root() 2102995Ssaidi@eecs.umich.edu self.testsys = testSystem 2112995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 2124981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 2134981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 2144981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 2154981Ssaidi@eecs.umich.edu 2163025Ssaidi@eecs.umich.edu if dumpfile: 2173025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 2183025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 2192934Sktlim@umich.edu 2202934Sktlim@umich.edu return self 2215253Sksewell@umich.edu 2225263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 2235253Sksewell@umich.edu #CP0 Configuration 2245253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 2255253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 2265253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 2275253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 2285253Sksewell@umich.edu 2295253Sksewell@umich.edu #CP0 Interrupt Control 2305253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 2315253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 2325253Sksewell@umich.edu 2335253Sksewell@umich.edu # Config Register 2345253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 2355253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 2365253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 2375253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 2385253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 2395253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 2405253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 2415253Sksewell@umich.edu 2425253Sksewell@umich.edu #Config 1 Register 2435253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 2445253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 2455253Sksewell@umich.edu # ***VERY IMPORTANT*** 2465253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 2475253Sksewell@umich.edu # Examine file ../common/Cache.py 2485253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 2495253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 2505253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 2515253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 2525253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 2535253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 2545253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 2555253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 2565253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 2575253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 2585253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 2595253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 2605253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 2615253Sksewell@umich.edu 2625253Sksewell@umich.edu #Config 2 Register 2635253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 2645253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 2655253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 2665253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 2675253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 2685253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 2695253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 2705253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 2715253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 2725253Sksewell@umich.edu 2735253Sksewell@umich.edu 2745253Sksewell@umich.edu #Config 3 Register 2755253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 2765253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 2775253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 2785253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 2795253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 2805253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 2815253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 2825253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 2835253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 2845253Sksewell@umich.edu 2855253Sksewell@umich.edu #SRS Ctl - HSS 2865253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 2875253Sksewell@umich.edu 2885253Sksewell@umich.edu 2895253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 2905253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 291