FSConfig.py revision 2995
12934Sktlim@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 22934Sktlim@umich.edu# All rights reserved. 32934Sktlim@umich.edu# 42934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132934Sktlim@umich.edu# this software without specific prior written permission. 142934Sktlim@umich.edu# 152934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# Authors: Kevin Lim 282934Sktlim@umich.edu 292934Sktlim@umich.eduimport m5 302969Sktlim@umich.edufrom m5 import makeList 312934Sktlim@umich.edufrom m5.objects import * 322995Ssaidi@eecs.umich.edufrom Benchmarks import * 332934Sktlim@umich.edufrom FullO3Config import * 342934Sktlim@umich.edufrom Util import * 352934Sktlim@umich.edu 362934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 372934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 382934Sktlim@umich.edu read_only=False) 392934Sktlim@umich.edu 402934Sktlim@umich.edu def childImage(self, ci): 412934Sktlim@umich.edu self.image.child.image_file = ci 422934Sktlim@umich.edu 432934Sktlim@umich.educlass BaseTsunami(Tsunami): 442934Sktlim@umich.edu ethernet = NSGigE(configdata=NSGigEPciData(), 452934Sktlim@umich.edu pci_bus=0, pci_dev=1, pci_func=0) 462934Sktlim@umich.edu etherint = NSGigEInt(device=Parent.ethernet) 472934Sktlim@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 482934Sktlim@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 492934Sktlim@umich.edu 502995Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache=None): 512934Sktlim@umich.edu self = LinuxAlphaSystem() 522995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 532934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 542934Sktlim@umich.edu self.membus = Bus(bus_id=1) 552934Sktlim@umich.edu self.bridge = Bridge() 562995Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 572934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 582934Sktlim@umich.edu self.bridge.side_b = self.membus.port 592934Sktlim@umich.edu self.physmem.port = self.membus.port 602934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 612934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 622995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 632934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 642934Sktlim@umich.edu self.tsunami = BaseTsunami() 652934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 662934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 672934Sktlim@umich.edu self.tsunami.ide.dma = self.iobus.port 682934Sktlim@umich.edu self.tsunami.ide.config = self.iobus.port 692934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 702934Sktlim@umich.edu self.tsunami.ethernet.dma = self.iobus.port 712934Sktlim@umich.edu self.tsunami.ethernet.config = self.iobus.port 722995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 732934Sktlim@umich.edu read_only = True)) 742934Sktlim@umich.edu self.intrctrl = IntrControl() 752934Sktlim@umich.edu self.cpu = cpu 762953Sktlim@umich.edu self.mem_mode = mem_mode 772934Sktlim@umich.edu connectCpu(self.cpu, self.membus, icache, dcache, l2cache) 782969Sktlim@umich.edu for each_cpu in makeList(self.cpu): 792934Sktlim@umich.edu each_cpu.itb = AlphaITB() 802934Sktlim@umich.edu each_cpu.dtb = AlphaDTB() 812934Sktlim@umich.edu self.cpu.clock = '2GHz' 822934Sktlim@umich.edu self.sim_console = SimConsole(listener=ConsoleListener(port=3456)) 832934Sktlim@umich.edu self.kernel = binary('vmlinux') 842934Sktlim@umich.edu self.pal = binary('ts_osfpal') 852934Sktlim@umich.edu self.console = binary('console') 862934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 872934Sktlim@umich.edu 882934Sktlim@umich.edu return self 892934Sktlim@umich.edu 902995Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem): 912934Sktlim@umich.edu self = Root() 922995Ssaidi@eecs.umich.edu self.testsys = testSystem 932995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 942934Sktlim@umich.edu 952934Sktlim@umich.edu self.etherdump = EtherDump(file='ethertrace') 962995Ssaidi@eecs.umich.edu self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0], 972995Ssaidi@eecs.umich.edu int2 = Parent.drivesys.tsunami.etherint[0], 982934Sktlim@umich.edu dump = Parent.etherdump) 992934Sktlim@umich.edu self.clock = '1THz' 1002934Sktlim@umich.edu return self 101