FSConfig.py revision 2934
12068SN/A# Copyright (c) 2006 The Regents of The University of Michigan 22068SN/A# All rights reserved. 32068SN/A# 42068SN/A# Redistribution and use in source and binary forms, with or without 52068SN/A# modification, are permitted provided that the following conditions are 62068SN/A# met: redistributions of source code must retain the above copyright 72068SN/A# notice, this list of conditions and the following disclaimer; 82068SN/A# redistributions in binary form must reproduce the above copyright 92068SN/A# notice, this list of conditions and the following disclaimer in the 102068SN/A# documentation and/or other materials provided with the distribution; 112068SN/A# neither the name of the copyright holders nor the names of its 122068SN/A# contributors may be used to endorse or promote products derived from 132068SN/A# this software without specific prior written permission. 142068SN/A# 152068SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162068SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172068SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182068SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192068SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202068SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212068SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222068SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232068SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242068SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252068SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262068SN/A# 272068SN/A# Authors: Kevin Lim 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduimport m5 302068SN/Afrom m5.objects import * 312649Ssaidi@eecs.umich.edufrom FullO3Config import * 322649Ssaidi@eecs.umich.edufrom SysPaths import * 332649Ssaidi@eecs.umich.edufrom Util import * 342649Ssaidi@eecs.umich.edu 352649Ssaidi@eecs.umich.eduscript.dir = '/z/saidi/work/m5.newmem/configs/boot' 362068SN/Alinux_image = env.get('LINUX_IMAGE', disk('linux-latest.img')) 372068SN/A 382068SN/Aclass CowIdeDisk(IdeDisk): 392068SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 402068SN/A read_only=False) 412068SN/A 422068SN/A def childImage(self, ci): 432068SN/A self.image.child.image_file = ci 442068SN/A 452068SN/Aclass BaseTsunami(Tsunami): 462068SN/A ethernet = NSGigE(configdata=NSGigEPciData(), 472068SN/A pci_bus=0, pci_dev=1, pci_func=0) 482068SN/A etherint = NSGigEInt(device=Parent.ethernet) 492068SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 502068SN/A pci_func=0, pci_dev=0, pci_bus=0) 512068SN/A 522068SN/Adef MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None): 532068SN/A self = LinuxAlphaSystem() 542068SN/A self.iobus = Bus(bus_id=0) 552068SN/A self.membus = Bus(bus_id=1) 562227SN/A self.bridge = Bridge() 572068SN/A self.physmem = PhysicalMemory(range = AddrRange('128MB')) 582068SN/A self.bridge.side_a = self.iobus.port 592068SN/A self.bridge.side_b = self.membus.port 602068SN/A self.physmem.port = self.membus.port 612068SN/A self.disk0 = CowIdeDisk(driveID='master') 622068SN/A self.disk2 = CowIdeDisk(driveID='master') 632068SN/A self.disk0.childImage(linux_image) 642068SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 652068SN/A self.tsunami = BaseTsunami() 662068SN/A self.tsunami.attachIO(self.iobus) 672068SN/A self.tsunami.ide.pio = self.iobus.port 682068SN/A self.tsunami.ide.dma = self.iobus.port 692068SN/A self.tsunami.ide.config = self.iobus.port 702068SN/A self.tsunami.ethernet.pio = self.iobus.port 712068SN/A self.tsunami.ethernet.dma = self.iobus.port 722068SN/A self.tsunami.ethernet.config = self.iobus.port 732068SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image, 742068SN/A read_only = True)) 752068SN/A self.intrctrl = IntrControl() 762068SN/A self.cpu = cpu 772068SN/A 782227SN/A connectCpu(self.cpu, self.membus, icache, dcache, l2cache) 792068SN/A for each_cpu in listWrapper(self.cpu): 802068SN/A each_cpu.itb = AlphaITB() 812068SN/A each_cpu.dtb = AlphaDTB() 822068SN/A self.cpu.clock = '2GHz' 832068SN/A self.sim_console = SimConsole(listener=ConsoleListener(port=3456)) 842068SN/A self.kernel = binary('vmlinux') 852068SN/A self.pal = binary('ts_osfpal') 862068SN/A self.console = binary('console') 872068SN/A self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 882068SN/A 892068SN/A return self 902068SN/A 912068SN/Aclass TsunamiRoot(Root): 922068SN/A pass 932068SN/A 942068SN/Adef DualRoot(clientSystem, serverSystem): 952068SN/A self = Root() 962068SN/A self.client = clientSystem 972068SN/A self.server = serverSystem 982068SN/A 992068SN/A self.etherdump = EtherDump(file='ethertrace') 1002068SN/A self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0], 1012068SN/A int2 = Parent.server.tsunami.etherint[0], 1022068SN/A dump = Parent.etherdump) 1032227SN/A self.clock = '1THz' 1042068SN/A return self 1052068SN/A