FSConfig.py revision 13606
113606Sciro.santilli@arm.com# Copyright (c) 2010-2012, 2015-2019 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 4212564Sgabeblack@google.comfrom __future__ import print_function 4312564Sgabeblack@google.com 442934Sktlim@umich.edufrom m5.objects import * 452995Ssaidi@eecs.umich.edufrom Benchmarks import * 4610046Snilay@cs.wisc.edufrom m5.util import * 4711688Sandreas.hansson@arm.comfrom common import PlatformConfig 482934Sktlim@umich.edu 4910747SChris.Emmons@arm.com# Populate to reflect supported os types per target ISA 5010747SChris.Emmons@arm.comos_types = { 'alpha' : [ 'linux' ], 5110747SChris.Emmons@arm.com 'mips' : [ 'linux' ], 5210747SChris.Emmons@arm.com 'sparc' : [ 'linux' ], 5310747SChris.Emmons@arm.com 'x86' : [ 'linux' ], 5410747SChris.Emmons@arm.com 'arm' : [ 'linux', 5510747SChris.Emmons@arm.com 'android-gingerbread', 5610747SChris.Emmons@arm.com 'android-ics', 5710747SChris.Emmons@arm.com 'android-jellybean', 5812026Sweipingliao@google.com 'android-kitkat', 5912026Sweipingliao@google.com 'android-nougat', ], 6010747SChris.Emmons@arm.com } 6110747SChris.Emmons@arm.com 622934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 632934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 642934Sktlim@umich.edu read_only=False) 652934Sktlim@umich.edu 662934Sktlim@umich.edu def childImage(self, ci): 672934Sktlim@umich.edu self.image.child.image_file = ci 682934Sktlim@umich.edu 6910720Sandreas.hansson@arm.comclass MemBus(SystemXBar): 706122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 716122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 726122SSteve.Reinhardt@amd.com 7310594Sgabeblack@google.comdef fillInCmdline(mdesc, template, **kwargs): 7410594Sgabeblack@google.com kwargs.setdefault('disk', mdesc.disk()) 7510697SCurtis.Dunham@arm.com kwargs.setdefault('rootdev', mdesc.rootdev()) 7610594Sgabeblack@google.com kwargs.setdefault('mem', mdesc.mem()) 7710594Sgabeblack@google.com kwargs.setdefault('script', mdesc.script()) 7810594Sgabeblack@google.com return template % kwargs 7910594Sgabeblack@google.com 8010594Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 8110118Snilay@cs.wisc.edu 824520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 834982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 844520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 854520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 862934Sktlim@umich.edu 872934Sktlim@umich.edu self = LinuxAlphaSystem() 883005Sstever@eecs.umich.edu if not mdesc: 893005Sstever@eecs.umich.edu # generic system 903304Sstever@eecs.umich.edu mdesc = SysConfig() 912995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 9210118Snilay@cs.wisc.edu 9310118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 9410118Snilay@cs.wisc.edu 9510118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 9610720Sandreas.hansson@arm.com self.iobus = IOXBar() 9710118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 9810118Snilay@cs.wisc.edu 9910118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 10010118Snilay@cs.wisc.edu 10110118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 10210118Snilay@cs.wisc.edu 10310118Snilay@cs.wisc.edu if ruby: 10410118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 10510118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 10610118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 10710118Snilay@cs.wisc.edu else: 10810118Snilay@cs.wisc.edu self.membus = MemBus() 10910118Snilay@cs.wisc.edu 11010118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 11110118Snilay@cs.wisc.edu # base address (including the PCI config space) 11210118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 11310118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 1148713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 11510118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 11610118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 11710118Snilay@cs.wisc.edu 11810118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 11910118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 12010118Snilay@cs.wisc.edu 12110118Snilay@cs.wisc.edu self.system_port = self.membus.slave 12210118Snilay@cs.wisc.edu 1239826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1242934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1252934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1262995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1272934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1286765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1296765SBrad.Beckmann@amd.com read_only = True)) 1306765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1316765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1326765SBrad.Beckmann@amd.com self.terminal = Terminal() 1336765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1346765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1356765SBrad.Beckmann@amd.com self.console = binary('console') 13610594Sgabeblack@google.com if not cmdline: 13710594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 13810594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1396765SBrad.Beckmann@amd.com 1406765SBrad.Beckmann@amd.com return self 1416765SBrad.Beckmann@amd.com 14211182Spalle@lyckegaard.dkdef makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 1438713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1448713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1458713Sandreas.hansson@arm.com uart_pio_size = 8 1468713Sandreas.hansson@arm.com 1474486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1484486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1494486Sbinkertn@umich.edu read_only=False) 1504486Sbinkertn@umich.edu 1514486Sbinkertn@umich.edu def childImage(self, ci): 1524486Sbinkertn@umich.edu self.image.child.image_file = ci 1534486Sbinkertn@umich.edu 1543584Ssaidi@eecs.umich.edu self = SparcSystem() 1553584Ssaidi@eecs.umich.edu if not mdesc: 1563584Ssaidi@eecs.umich.edu # generic system 1573584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1583584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 15910720Sandreas.hansson@arm.com self.iobus = IOXBar() 1609036Sandreas.hansson@arm.com self.membus = MemBus() 1619164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1623743Sgblack@eecs.umich.edu self.t1000 = T1000() 1634104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1643743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1659826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1669826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1678839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1688839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1698839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1708839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1718839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1728839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1733584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1743898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 17511563Sjakub@jermar.eu self.disk0.childImage(mdesc.disk()) 1768839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1778713Sandreas.hansson@arm.com 1788713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1798713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1808713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1818713Sandreas.hansson@arm.com self.bridge.ranges = \ 1828713Sandreas.hansson@arm.com [ 1838713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1848713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1858713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1868713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1878713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1888713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1898713Sandreas.hansson@arm.com iob_man_addr - 1), 1908713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1918713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1928713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1938713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1948713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1958713Sandreas.hansson@arm.com ] 1964103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1974103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1984103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1993745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 2003745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 2013745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2023584Ssaidi@eecs.umich.edu 2038839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2048706Sandreas.hansson@arm.com 2053584Ssaidi@eecs.umich.edu return self 2063584Ssaidi@eecs.umich.edu 20710588Sgabeblack@google.comdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 20810780SCurtis.Dunham@arm.com dtb_filename=None, bare_metal=False, cmdline=None, 20913606Sciro.santilli@arm.com external_memory="", ruby=False, security=False): 2108061SAli.Saidi@ARM.com assert machine_type 2118061SAli.Saidi@ARM.com 21211297Sandreas.sandberg@arm.com pci_devices = [] 21311297Sandreas.sandberg@arm.com 2147586SAli.Saidi@arm.com if bare_metal: 2157586SAli.Saidi@arm.com self = ArmSystem() 2167586SAli.Saidi@arm.com else: 2177586SAli.Saidi@arm.com self = LinuxArmSystem() 2187586SAli.Saidi@arm.com 2197586SAli.Saidi@arm.com if not mdesc: 2207586SAli.Saidi@arm.com # generic system 2217586SAli.Saidi@arm.com mdesc = SysConfig() 2227586SAli.Saidi@arm.com 2237586SAli.Saidi@arm.com self.readfile = mdesc.script() 22410720Sandreas.hansson@arm.com self.iobus = IOXBar() 22511598Sandreas.sandberg@arm.com if not ruby: 22611598Sandreas.sandberg@arm.com self.bridge = Bridge(delay='50ns') 22711598Sandreas.sandberg@arm.com self.bridge.master = self.iobus.slave 22811598Sandreas.sandberg@arm.com self.membus = MemBus() 22911598Sandreas.sandberg@arm.com self.membus.badaddr_responder.warn_access = "warn" 23011598Sandreas.sandberg@arm.com self.bridge.slave = self.membus.master 2317586SAli.Saidi@arm.com 2327586SAli.Saidi@arm.com self.mem_mode = mem_mode 2337586SAli.Saidi@arm.com 23411238Sandreas.sandberg@arm.com platform_class = PlatformConfig.get(machine_type) 23511238Sandreas.sandberg@arm.com # Resolve the real platform name, the original machine_type 23611238Sandreas.sandberg@arm.com # variable might have been an alias. 23711238Sandreas.sandberg@arm.com machine_type = platform_class.__name__ 23811238Sandreas.sandberg@arm.com self.realview = platform_class() 23911238Sandreas.sandberg@arm.com 24011238Sandreas.sandberg@arm.com if isinstance(self.realview, VExpress_EMM64): 24110512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 24212564Sgabeblack@google.com print("Selected 64-bit ARM architecture, updating default " 24312564Sgabeblack@google.com "disk image...") 24410512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 2457586SAli.Saidi@arm.com 24610353SGeoffrey.Blake@arm.com 24710353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 24810353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 24911297Sandreas.sandberg@arm.com 25011297Sandreas.sandberg@arm.com self.cf0 = CowIdeDisk(driveID='master') 25111297Sandreas.sandberg@arm.com self.cf0.childImage(mdesc.disk()) 25211297Sandreas.sandberg@arm.com # Old platforms have a built-in IDE or CF controller. Default to 25311297Sandreas.sandberg@arm.com # the IDE controller if both exist. New platforms expect the 25411297Sandreas.sandberg@arm.com # storage controller to be added from the config script. 25511297Sandreas.sandberg@arm.com if hasattr(self.realview, "ide"): 25610357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 25711297Sandreas.sandberg@arm.com elif hasattr(self.realview, "cf_ctrl"): 2588528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 25911297Sandreas.sandberg@arm.com else: 26011297Sandreas.sandberg@arm.com self.pci_ide = IdeController(disks=[self.cf0]) 26111297Sandreas.sandberg@arm.com pci_devices.append(self.pci_ide) 2628528SAli.Saidi@ARM.com 26310507SAli.Saidi@ARM.com self.mem_ranges = [] 26410507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 26510507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 26610507SAli.Saidi@ARM.com if size_remain > long(region[1]): 26710507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 26810507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 26910507SAli.Saidi@ARM.com else: 27010507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 27110507SAli.Saidi@ARM.com size_remain = 0 27210507SAli.Saidi@ARM.com break 27310507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 27410507SAli.Saidi@ARM.com " another memory controller for that range.") 27510507SAli.Saidi@ARM.com 27610507SAli.Saidi@ARM.com if size_remain > 0: 27710507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 27810507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 27910507SAli.Saidi@ARM.com " another platform") 28010507SAli.Saidi@ARM.com 28112079Sgedare@rtems.org self.have_security = security 28212079Sgedare@rtems.org 2838061SAli.Saidi@ARM.com if bare_metal: 2848061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 28513015Sciro.santilli@arm.com self.realview.uart[0].end_on_eot = True 2868061SAli.Saidi@ARM.com else: 28713606Sciro.santilli@arm.com if dtb_filename: 2889929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 28911238Sandreas.sandberg@arm.com 29011238Sandreas.sandberg@arm.com self.machine_type = machine_type if machine_type in ArmMachineType.map \ 29111238Sandreas.sandberg@arm.com else "DTOnly" 29211238Sandreas.sandberg@arm.com 29310071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 29410594Sgabeblack@google.com if not cmdline: 29510594Sgabeblack@google.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 29610594Sgabeblack@google.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 29710697SCurtis.Dunham@arm.com 'mem=%(mem)s root=%(rootdev)s' 29810071Satgutier@umich.edu 29910780SCurtis.Dunham@arm.com # When using external memory, gem5 writes the boot loader to nvmem 30010780SCurtis.Dunham@arm.com # and then SST will read from it, but SST can only get to nvmem from 30110780SCurtis.Dunham@arm.com # iobus, as gem5's membus is only used for initialization and 30210780SCurtis.Dunham@arm.com # SST doesn't use it. Attaching nvmem to iobus solves this issue. 30310780SCurtis.Dunham@arm.com # During initialization, system_port -> membus -> iobus -> nvmem. 30412598Snikos.nikoleris@arm.com if external_memory: 30510780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.iobus, self, binary) 30612598Snikos.nikoleris@arm.com elif ruby: 30712598Snikos.nikoleris@arm.com self.realview.setupBootLoader(None, self, binary) 30810780SCurtis.Dunham@arm.com else: 30910780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.membus, self, binary) 31013532Sjairo.balart@metempsy.com 31113532Sjairo.balart@metempsy.com if hasattr(self.realview.gic, 'cpu_addr'): 31213532Sjairo.balart@metempsy.com self.gic_cpu_addr = self.realview.gic.cpu_addr 31313532Sjairo.balart@metempsy.com 3148528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 3158287SAli.Saidi@ARM.com 31610747SChris.Emmons@arm.com # This check is for users who have previously put 'android' in 31710747SChris.Emmons@arm.com # the disk image filename to tell the config scripts to 31810747SChris.Emmons@arm.com # prepare the kernel with android-specific boot options. That 31910747SChris.Emmons@arm.com # behavior has been replaced with a more explicit option per 32010747SChris.Emmons@arm.com # the error message below. The disk can have any name now and 32110747SChris.Emmons@arm.com # doesn't need to include 'android' substring. 32210735Srb639@drexel.edu if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 32310747SChris.Emmons@arm.com if 'android' not in mdesc.os_type(): 32410747SChris.Emmons@arm.com fatal("It looks like you are trying to boot an Android " \ 32510747SChris.Emmons@arm.com "platform. To boot Android, you must specify " \ 32610747SChris.Emmons@arm.com "--os-type with an appropriate Android release on " \ 32710747SChris.Emmons@arm.com "the command line.") 32810747SChris.Emmons@arm.com 32910747SChris.Emmons@arm.com # android-specific tweaks 33010747SChris.Emmons@arm.com if 'android' in mdesc.os_type(): 33110747SChris.Emmons@arm.com # generic tweaks 33210747SChris.Emmons@arm.com cmdline += " init=/init" 33310747SChris.Emmons@arm.com 33410747SChris.Emmons@arm.com # release-specific tweaks 33510747SChris.Emmons@arm.com if 'kitkat' in mdesc.os_type(): 33610747SChris.Emmons@arm.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 33712026Sweipingliao@google.com "android.bootanim=0 " 33812026Sweipingliao@google.com elif 'nougat' in mdesc.os_type(): 33912026Sweipingliao@google.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 34012026Sweipingliao@google.com "android.bootanim=0 " + \ 34112026Sweipingliao@google.com "vmalloc=640MB " + \ 34212026Sweipingliao@google.com "android.early.fstab=/fstab.gem5 " + \ 34312026Sweipingliao@google.com "androidboot.selinux=permissive " + \ 34412026Sweipingliao@google.com "video=Virtual-1:1920x1080-16" 34510747SChris.Emmons@arm.com 34610594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 34710747SChris.Emmons@arm.com 34810780SCurtis.Dunham@arm.com if external_memory: 34910780SCurtis.Dunham@arm.com # I/O traffic enters iobus 35010780SCurtis.Dunham@arm.com self.external_io = ExternalMaster(port_data="external_io", 35110780SCurtis.Dunham@arm.com port_type=external_memory) 35210780SCurtis.Dunham@arm.com self.external_io.port = self.iobus.slave 35310780SCurtis.Dunham@arm.com 35410780SCurtis.Dunham@arm.com # Ensure iocache only receives traffic destined for (actual) memory. 35510780SCurtis.Dunham@arm.com self.iocache = ExternalSlave(port_data="iocache", 35610780SCurtis.Dunham@arm.com port_type=external_memory, 35710780SCurtis.Dunham@arm.com addr_ranges=self.mem_ranges) 35810780SCurtis.Dunham@arm.com self.iocache.port = self.iobus.master 35910780SCurtis.Dunham@arm.com 36010780SCurtis.Dunham@arm.com # Let system_port get to nvmem and nothing else. 36110780SCurtis.Dunham@arm.com self.bridge.ranges = [self.realview.nvmem.range] 36210780SCurtis.Dunham@arm.com 36310780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.iobus) 36411598Sandreas.sandberg@arm.com # Attach off-chip devices 36511598Sandreas.sandberg@arm.com self.realview.attachIO(self.iobus) 36611598Sandreas.sandberg@arm.com elif ruby: 36711598Sandreas.sandberg@arm.com self._dma_ports = [ ] 36811598Sandreas.sandberg@arm.com self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 36911598Sandreas.sandberg@arm.com self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 37010780SCurtis.Dunham@arm.com else: 37110780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 37211598Sandreas.sandberg@arm.com # Attach off-chip devices 37311598Sandreas.sandberg@arm.com self.realview.attachIO(self.iobus) 37411297Sandreas.sandberg@arm.com 37511297Sandreas.sandberg@arm.com for dev_id, dev in enumerate(pci_devices): 37611297Sandreas.sandberg@arm.com dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 37711598Sandreas.sandberg@arm.com self.realview.attachPciDevice( 37811598Sandreas.sandberg@arm.com dev, self.iobus, 37911598Sandreas.sandberg@arm.com dma_ports=self._dma_ports if ruby else None) 38011297Sandreas.sandberg@arm.com 3817586SAli.Saidi@arm.com self.intrctrl = IntrControl() 3827586SAli.Saidi@arm.com self.terminal = Terminal() 3837949SAli.Saidi@ARM.com self.vncserver = VncServer() 3847586SAli.Saidi@arm.com 38511598Sandreas.sandberg@arm.com if not ruby: 38611598Sandreas.sandberg@arm.com self.system_port = self.membus.slave 3878706Sandreas.hansson@arm.com 38811599Sandreas.sandberg@arm.com if ruby: 38912067Snikos.nikoleris@arm.com if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 39012067Snikos.nikoleris@arm.com fatal("The MI_example protocol cannot implement Load/Store " 39112067Snikos.nikoleris@arm.com "Exclusive operations. Multicore ARM systems configured " 39212067Snikos.nikoleris@arm.com "with the MI_example protocol will not work properly.") 39312067Snikos.nikoleris@arm.com warn("You are trying to use Ruby on ARM, which is not working " 39412067Snikos.nikoleris@arm.com "properly yet.") 39511599Sandreas.sandberg@arm.com 3967586SAli.Saidi@arm.com return self 3977586SAli.Saidi@arm.com 3987586SAli.Saidi@arm.com 39910594Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 4005222Sksewell@umich.edu class BaseMalta(Malta): 4015222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 4025222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 4035222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 4045222Sksewell@umich.edu 4055222Sksewell@umich.edu self = LinuxMipsSystem() 4065222Sksewell@umich.edu if not mdesc: 4075222Sksewell@umich.edu # generic system 4085222Sksewell@umich.edu mdesc = SysConfig() 4095222Sksewell@umich.edu self.readfile = mdesc.script() 41010720Sandreas.hansson@arm.com self.iobus = IOXBar() 4119036Sandreas.hansson@arm.com self.membus = MemBus() 4129164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 4139826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 4148839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 4158839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 4165222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 4175222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 4185222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 4195222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 4205222Sksewell@umich.edu self.malta = BaseMalta() 4215222Sksewell@umich.edu self.malta.attachIO(self.iobus) 4228839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 4238839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 4248839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 4258839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 4265222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 4275222Sksewell@umich.edu read_only = True)) 4285222Sksewell@umich.edu self.intrctrl = IntrControl() 4295222Sksewell@umich.edu self.mem_mode = mem_mode 4305478Snate@binkert.org self.terminal = Terminal() 4315222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 4325222Sksewell@umich.edu self.console = binary('mips/console') 43310594Sgabeblack@google.com if not cmdline: 43410594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 43510594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 4365222Sksewell@umich.edu 4378839Sandreas.hansson@arm.com self.system_port = self.membus.slave 4388706Sandreas.hansson@arm.com 4395222Sksewell@umich.edu return self 4405222Sksewell@umich.edu 4415323Sgblack@eecs.umich.edudef x86IOAddress(port): 4425357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 4438323Ssteve.reinhardt@amd.com return IO_address_space_base + port 4445323Sgblack@eecs.umich.edu 4458858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 4468713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 4478713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 4488713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 4498713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 4508713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 4518713Sandreas.hansson@arm.com 4529036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 4537905SBrad.Beckmann@amd.com 4547905SBrad.Beckmann@amd.com # North Bridge 45510720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4569164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 4578839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 4588839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 45910438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 46010438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 46110438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 46210438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 46310438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 46410438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 4658713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 4668713Sandreas.hansson@arm.com [ 46710438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 4688713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 4698713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 4708713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 4718713Sandreas.hansson@arm.com Addr.max) 4728713Sandreas.hansson@arm.com ] 4738713Sandreas.hansson@arm.com 4748713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 4758713Sandreas.hansson@arm.com # the local APIC (two pages) 4769164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 4778839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 4788839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 4798815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 4808815Sgblack@eecs.umich.edu interrupts_address_space_base + 4818858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 4828858Sgblack@eecs.umich.edu - 1)] 4837905SBrad.Beckmann@amd.com 4847905SBrad.Beckmann@amd.com # connect the io bus 4857905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 4867905SBrad.Beckmann@amd.com 4878839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 4888706Sandreas.hansson@arm.com 4897905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 4907905SBrad.Beckmann@amd.com # North Bridge 49110720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4927905SBrad.Beckmann@amd.com 4938929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 4948929Snilay@cs.wisc.edu # dma controllers 4958929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 49610118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 4977905SBrad.Beckmann@amd.com 4987905SBrad.Beckmann@amd.com 49910588Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 5005613Sgblack@eecs.umich.edu if self == None: 5015613Sgblack@eecs.umich.edu self = X86System() 5025613Sgblack@eecs.umich.edu 5035133Sgblack@eecs.umich.edu if not mdesc: 5045133Sgblack@eecs.umich.edu # generic system 5055133Sgblack@eecs.umich.edu mdesc = SysConfig() 5065133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 5075133Sgblack@eecs.umich.edu 5086802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 5096802Sgblack@eecs.umich.edu 5105133Sgblack@eecs.umich.edu # Physical memory 51110041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 51210041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 51310041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 51410041Snilay@cs.wisc.edu excess_mem_size = \ 51510041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 51610041Snilay@cs.wisc.edu if excess_mem_size <= 0: 51710041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 51810041Snilay@cs.wisc.edu else: 51910046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 52010046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 52110046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 52210046Snilay@cs.wisc.edu 52310041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 52410041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 5255613Sgblack@eecs.umich.edu 5265613Sgblack@eecs.umich.edu # Platform 5275638Sgblack@eecs.umich.edu self.pc = Pc() 5287905SBrad.Beckmann@amd.com 5297905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 5307905SBrad.Beckmann@amd.com if Ruby: 5317905SBrad.Beckmann@amd.com connectX86RubySystem(self) 5327905SBrad.Beckmann@amd.com else: 5338858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 5345613Sgblack@eecs.umich.edu 5355613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 5365613Sgblack@eecs.umich.edu 5375841Sgblack@eecs.umich.edu # Disks 5385841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 5395841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 5405841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 5415841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 5425841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 5435841Sgblack@eecs.umich.edu 5445615Sgblack@eecs.umich.edu # Add in a Bios information structure. 5455615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 5465615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 5475615Sgblack@eecs.umich.edu 5485641Sgblack@eecs.umich.edu # Set up the Intel MP table 5498323Ssteve.reinhardt@amd.com base_entries = [] 5508323Ssteve.reinhardt@amd.com ext_entries = [] 5516135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 5526135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 5536135Sgblack@eecs.umich.edu local_apic_id = i, 5546135Sgblack@eecs.umich.edu local_apic_version = 0x14, 5556135Sgblack@eecs.umich.edu enable = True, 5566135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 5578323Ssteve.reinhardt@amd.com base_entries.append(bp) 5585644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 5596135Sgblack@eecs.umich.edu id = numCPUs, 5605644Sgblack@eecs.umich.edu version = 0x11, 5615644Sgblack@eecs.umich.edu enable = True, 5625644Sgblack@eecs.umich.edu address = 0xfec00000) 5636135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 5648323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 56510437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 56610437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 56710437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 56811481Sbaz21@cam.ac.uk pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 56910437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 57011481Sbaz21@cam.ac.uk isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 5718323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 57210437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 57310437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 5748323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 5755843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 5765843Sgblack@eecs.umich.edu interrupt_type = 'INT', 5775843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5785843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 57910437Smajiuyue@ncic.ac.cn source_bus_id = 0, 5805843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 5816044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5825843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 5838323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 5846135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 5856135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 5866135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 5876135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5886135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 58910437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5906135Sgblack@eecs.umich.edu source_bus_irq = irq, 5916135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5926135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 5938323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 5946135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 5956135Sgblack@eecs.umich.edu interrupt_type = 'INT', 5966135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5976135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 59810437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5996135Sgblack@eecs.umich.edu source_bus_irq = irq, 6006135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 6016135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 6028323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 6036135Sgblack@eecs.umich.edu assignISAInt(0, 2) 6046135Sgblack@eecs.umich.edu assignISAInt(1, 1) 6056135Sgblack@eecs.umich.edu for i in range(3, 15): 6066135Sgblack@eecs.umich.edu assignISAInt(i, i) 6078323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 6088323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 6095641Sgblack@eecs.umich.edu 61010594Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 61110594Sgabeblack@google.com cmdline=None): 6125613Sgblack@eecs.umich.edu self = LinuxX86System() 6135613Sgblack@eecs.umich.edu 6147905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 6159826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 6165613Sgblack@eecs.umich.edu 6175450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 6185450Sgblack@eecs.umich.edu # just to avoid corner cases. 6199826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 6209232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 62110041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 6225450Sgblack@eecs.umich.edu 62310041Snilay@cs.wisc.edu entries = \ 6248323Ssteve.reinhardt@amd.com [ 6258323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 6269622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 6279622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 62810041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 6298323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 63010041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 6319898Sandreas@sandberg.pp.se range_type = 1), 6328323Ssteve.reinhardt@amd.com ] 6335450Sgblack@eecs.umich.edu 63410438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 63510438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 63610438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 63710438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 63810438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 63910438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 64010438Smajiuyue@ncic.ac.cn range_type=2)) 64110438Smajiuyue@ncic.ac.cn 64210438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 64310438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 64410438Smajiuyue@ncic.ac.cn 64510041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 64610041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 64710041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 64810041Snilay@cs.wisc.edu # reserved for devices. 64910041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 65010041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 65110041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 65210041Snilay@cs.wisc.edu 65310041Snilay@cs.wisc.edu self.e820_table.entries = entries 65410041Snilay@cs.wisc.edu 6555330Sgblack@eecs.umich.edu # Command line 65610594Sgabeblack@google.com if not cmdline: 65710594Sgabeblack@google.com cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 65810594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 65910003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 6605133Sgblack@eecs.umich.edu return self 6615133Sgblack@eecs.umich.edu 6623584Ssaidi@eecs.umich.edu 6638801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 6648801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 6652995Ssaidi@eecs.umich.edu self.testsys = testSystem 6662995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 6674981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 6684981Ssaidi@eecs.umich.edu 6698661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 6708661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 6718661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 6728661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 6738661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 6748661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 6758661SAli.Saidi@ARM.com else: 6768661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 6778661SAli.Saidi@ARM.com 6783025Ssaidi@eecs.umich.edu if dumpfile: 6793025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 6803025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 6812934Sktlim@umich.edu 6822934Sktlim@umich.edu return self 68311291Sgabor.dozsa@arm.com 68411291Sgabor.dozsa@arm.com 68511291Sgabor.dozsa@arm.comdef makeDistRoot(testSystem, 68611291Sgabor.dozsa@arm.com rank, 68711291Sgabor.dozsa@arm.com size, 68811291Sgabor.dozsa@arm.com server_name, 68911291Sgabor.dozsa@arm.com server_port, 69011291Sgabor.dozsa@arm.com sync_repeat, 69111291Sgabor.dozsa@arm.com sync_start, 69211291Sgabor.dozsa@arm.com linkspeed, 69311291Sgabor.dozsa@arm.com linkdelay, 69411291Sgabor.dozsa@arm.com dumpfile): 69511291Sgabor.dozsa@arm.com self = Root(full_system = True) 69611291Sgabor.dozsa@arm.com self.testsys = testSystem 69711291Sgabor.dozsa@arm.com 69811291Sgabor.dozsa@arm.com self.etherlink = DistEtherLink(speed = linkspeed, 69911291Sgabor.dozsa@arm.com delay = linkdelay, 70011291Sgabor.dozsa@arm.com dist_rank = rank, 70111291Sgabor.dozsa@arm.com dist_size = size, 70211291Sgabor.dozsa@arm.com server_name = server_name, 70311291Sgabor.dozsa@arm.com server_port = server_port, 70411291Sgabor.dozsa@arm.com sync_start = sync_start, 70511291Sgabor.dozsa@arm.com sync_repeat = sync_repeat) 70611291Sgabor.dozsa@arm.com 70711291Sgabor.dozsa@arm.com if hasattr(testSystem, 'realview'): 70811291Sgabor.dozsa@arm.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 70911291Sgabor.dozsa@arm.com elif hasattr(testSystem, 'tsunami'): 71011291Sgabor.dozsa@arm.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 71111291Sgabor.dozsa@arm.com else: 71211291Sgabor.dozsa@arm.com fatal("Don't know how to connect DistEtherLink to this system") 71311291Sgabor.dozsa@arm.com 71411291Sgabor.dozsa@arm.com if dumpfile: 71511291Sgabor.dozsa@arm.com self.etherdump = EtherDump(file=dumpfile) 71611291Sgabor.dozsa@arm.com self.etherlink.dump = Parent.etherdump 71711291Sgabor.dozsa@arm.com 71811291Sgabor.dozsa@arm.com return self 719