FSConfig.py revision 11291
110780SCurtis.Dunham@arm.com# Copyright (c) 2010-2012, 2015 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 4511238Sandreas.sandberg@arm.comimport PlatformConfig 462934Sktlim@umich.edu 4710747SChris.Emmons@arm.com# Populate to reflect supported os types per target ISA 4810747SChris.Emmons@arm.comos_types = { 'alpha' : [ 'linux' ], 4910747SChris.Emmons@arm.com 'mips' : [ 'linux' ], 5010747SChris.Emmons@arm.com 'sparc' : [ 'linux' ], 5110747SChris.Emmons@arm.com 'x86' : [ 'linux' ], 5210747SChris.Emmons@arm.com 'arm' : [ 'linux', 5310747SChris.Emmons@arm.com 'android-gingerbread', 5410747SChris.Emmons@arm.com 'android-ics', 5510747SChris.Emmons@arm.com 'android-jellybean', 5610747SChris.Emmons@arm.com 'android-kitkat' ], 5710747SChris.Emmons@arm.com } 5810747SChris.Emmons@arm.com 592934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 602934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 612934Sktlim@umich.edu read_only=False) 622934Sktlim@umich.edu 632934Sktlim@umich.edu def childImage(self, ci): 642934Sktlim@umich.edu self.image.child.image_file = ci 652934Sktlim@umich.edu 6610720Sandreas.hansson@arm.comclass MemBus(SystemXBar): 676122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 686122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 696122SSteve.Reinhardt@amd.com 7010594Sgabeblack@google.comdef fillInCmdline(mdesc, template, **kwargs): 7110594Sgabeblack@google.com kwargs.setdefault('disk', mdesc.disk()) 7210697SCurtis.Dunham@arm.com kwargs.setdefault('rootdev', mdesc.rootdev()) 7310594Sgabeblack@google.com kwargs.setdefault('mem', mdesc.mem()) 7410594Sgabeblack@google.com kwargs.setdefault('script', mdesc.script()) 7510594Sgabeblack@google.com return template % kwargs 7610594Sgabeblack@google.com 7710594Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 7810118Snilay@cs.wisc.edu 794520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 804982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 814520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 824520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 832934Sktlim@umich.edu 842934Sktlim@umich.edu self = LinuxAlphaSystem() 853005Sstever@eecs.umich.edu if not mdesc: 863005Sstever@eecs.umich.edu # generic system 873304Sstever@eecs.umich.edu mdesc = SysConfig() 882995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 8910118Snilay@cs.wisc.edu 9010118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 9110118Snilay@cs.wisc.edu 9210118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 9310720Sandreas.hansson@arm.com self.iobus = IOXBar() 9410118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 9510118Snilay@cs.wisc.edu 9610118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 9710118Snilay@cs.wisc.edu 9810118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 9910118Snilay@cs.wisc.edu 10010118Snilay@cs.wisc.edu if ruby: 10110118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 10210118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 10310118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 10410118Snilay@cs.wisc.edu else: 10510118Snilay@cs.wisc.edu self.membus = MemBus() 10610118Snilay@cs.wisc.edu 10710118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 10810118Snilay@cs.wisc.edu # base address (including the PCI config space) 10910118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 11010118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 1118713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 11210118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 11310118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 11410118Snilay@cs.wisc.edu 11510118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 11610118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 11710118Snilay@cs.wisc.edu 11810118Snilay@cs.wisc.edu self.system_port = self.membus.slave 11910118Snilay@cs.wisc.edu 1209826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1212934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1222934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1232995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1242934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1256765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1266765SBrad.Beckmann@amd.com read_only = True)) 1276765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1286765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1296765SBrad.Beckmann@amd.com self.terminal = Terminal() 1306765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1316765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1326765SBrad.Beckmann@amd.com self.console = binary('console') 13310594Sgabeblack@google.com if not cmdline: 13410594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 13510594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1366765SBrad.Beckmann@amd.com 1376765SBrad.Beckmann@amd.com return self 1386765SBrad.Beckmann@amd.com 13911182Spalle@lyckegaard.dkdef makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 1408713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1418713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1428713Sandreas.hansson@arm.com uart_pio_size = 8 1438713Sandreas.hansson@arm.com 1444486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1454486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1464486Sbinkertn@umich.edu read_only=False) 1474486Sbinkertn@umich.edu 1484486Sbinkertn@umich.edu def childImage(self, ci): 1494486Sbinkertn@umich.edu self.image.child.image_file = ci 1504486Sbinkertn@umich.edu 1513584Ssaidi@eecs.umich.edu self = SparcSystem() 1523584Ssaidi@eecs.umich.edu if not mdesc: 1533584Ssaidi@eecs.umich.edu # generic system 1543584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1553584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 15610720Sandreas.hansson@arm.com self.iobus = IOXBar() 1579036Sandreas.hansson@arm.com self.membus = MemBus() 1589164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1593743Sgblack@eecs.umich.edu self.t1000 = T1000() 1604104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1613743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1629826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1639826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1648839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1658839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1668839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1678839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1688839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1698839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1703584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1713898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1723898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1738839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1748713Sandreas.hansson@arm.com 1758713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1768713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1778713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1788713Sandreas.hansson@arm.com self.bridge.ranges = \ 1798713Sandreas.hansson@arm.com [ 1808713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1818713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1828713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1838713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1848713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1858713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1868713Sandreas.hansson@arm.com iob_man_addr - 1), 1878713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1888713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1898713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1908713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1918713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1928713Sandreas.hansson@arm.com ] 1934103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1944103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1954103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1963745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1973745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1983745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1993584Ssaidi@eecs.umich.edu 2008839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2018706Sandreas.hansson@arm.com 2023584Ssaidi@eecs.umich.edu return self 2033584Ssaidi@eecs.umich.edu 20410588Sgabeblack@google.comdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 20510780SCurtis.Dunham@arm.com dtb_filename=None, bare_metal=False, cmdline=None, 20610780SCurtis.Dunham@arm.com external_memory=""): 2078061SAli.Saidi@ARM.com assert machine_type 2088061SAli.Saidi@ARM.com 20911238Sandreas.sandberg@arm.com default_dtbs = { 21011238Sandreas.sandberg@arm.com "RealViewEB": None, 21111238Sandreas.sandberg@arm.com "RealViewPBX": None, 21211238Sandreas.sandberg@arm.com "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 21311238Sandreas.sandberg@arm.com "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 21411238Sandreas.sandberg@arm.com } 21511238Sandreas.sandberg@arm.com 21611238Sandreas.sandberg@arm.com default_kernels = { 21711238Sandreas.sandberg@arm.com "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 21811238Sandreas.sandberg@arm.com "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 21911238Sandreas.sandberg@arm.com "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 22011238Sandreas.sandberg@arm.com "VExpress_EMM64": "vmlinux.aarch64.20140821", 22111238Sandreas.sandberg@arm.com } 22211238Sandreas.sandberg@arm.com 2237586SAli.Saidi@arm.com if bare_metal: 2247586SAli.Saidi@arm.com self = ArmSystem() 2257586SAli.Saidi@arm.com else: 2267586SAli.Saidi@arm.com self = LinuxArmSystem() 2277586SAli.Saidi@arm.com 2287586SAli.Saidi@arm.com if not mdesc: 2297586SAli.Saidi@arm.com # generic system 2307586SAli.Saidi@arm.com mdesc = SysConfig() 2317586SAli.Saidi@arm.com 2327586SAli.Saidi@arm.com self.readfile = mdesc.script() 23310720Sandreas.hansson@arm.com self.iobus = IOXBar() 2349036Sandreas.hansson@arm.com self.membus = MemBus() 2357586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2369164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2378839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2388839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2397586SAli.Saidi@arm.com 2407586SAli.Saidi@arm.com self.mem_mode = mem_mode 2417586SAli.Saidi@arm.com 24211238Sandreas.sandberg@arm.com platform_class = PlatformConfig.get(machine_type) 24311238Sandreas.sandberg@arm.com # Resolve the real platform name, the original machine_type 24411238Sandreas.sandberg@arm.com # variable might have been an alias. 24511238Sandreas.sandberg@arm.com machine_type = platform_class.__name__ 24611238Sandreas.sandberg@arm.com self.realview = platform_class() 24711238Sandreas.sandberg@arm.com 24811238Sandreas.sandberg@arm.com if not dtb_filename and not bare_metal: 24911238Sandreas.sandberg@arm.com try: 25011238Sandreas.sandberg@arm.com dtb_filename = default_dtbs[machine_type] 25111238Sandreas.sandberg@arm.com except KeyError: 25211238Sandreas.sandberg@arm.com fatal("No DTB specified and no default DTB known for '%s'" % \ 25311238Sandreas.sandberg@arm.com machine_type) 25411238Sandreas.sandberg@arm.com 25511238Sandreas.sandberg@arm.com if isinstance(self.realview, VExpress_EMM64): 25610512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 25710512SAli.Saidi@ARM.com print "Selected 64-bit ARM architecture, updating default disk image..." 25810512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 2597586SAli.Saidi@arm.com 2608528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2618528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 26210353SGeoffrey.Blake@arm.com 26310353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 26410353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 2658528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 26610357SAli.Saidi@ARM.com try: 26710357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 26810357SAli.Saidi@ARM.com except: 2698528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2708528SAli.Saidi@ARM.com 27110507SAli.Saidi@ARM.com self.mem_ranges = [] 27210507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 27310507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 27410507SAli.Saidi@ARM.com if size_remain > long(region[1]): 27510507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 27610507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 27710507SAli.Saidi@ARM.com else: 27810507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 27910507SAli.Saidi@ARM.com size_remain = 0 28010507SAli.Saidi@ARM.com break 28110507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 28210507SAli.Saidi@ARM.com " another memory controller for that range.") 28310507SAli.Saidi@ARM.com 28410507SAli.Saidi@ARM.com if size_remain > 0: 28510507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 28610507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 28710507SAli.Saidi@ARM.com " another platform") 28810507SAli.Saidi@ARM.com 2898061SAli.Saidi@ARM.com if bare_metal: 2908061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2918061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2928061SAli.Saidi@ARM.com else: 29311238Sandreas.sandberg@arm.com if machine_type in default_kernels: 29411238Sandreas.sandberg@arm.com self.kernel = binary(default_kernels[machine_type]) 29510161Satgutier@umich.edu 2969929SAli.Saidi@ARM.com if dtb_filename: 2979929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 29811238Sandreas.sandberg@arm.com 29911238Sandreas.sandberg@arm.com self.machine_type = machine_type if machine_type in ArmMachineType.map \ 30011238Sandreas.sandberg@arm.com else "DTOnly" 30111238Sandreas.sandberg@arm.com 30210071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 30310594Sgabeblack@google.com if not cmdline: 30410594Sgabeblack@google.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 30510594Sgabeblack@google.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 30610697SCurtis.Dunham@arm.com 'mem=%(mem)s root=%(rootdev)s' 30710071Satgutier@umich.edu 30810780SCurtis.Dunham@arm.com # When using external memory, gem5 writes the boot loader to nvmem 30910780SCurtis.Dunham@arm.com # and then SST will read from it, but SST can only get to nvmem from 31010780SCurtis.Dunham@arm.com # iobus, as gem5's membus is only used for initialization and 31110780SCurtis.Dunham@arm.com # SST doesn't use it. Attaching nvmem to iobus solves this issue. 31210780SCurtis.Dunham@arm.com # During initialization, system_port -> membus -> iobus -> nvmem. 31310780SCurtis.Dunham@arm.com if external_memory: 31410780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.iobus, self, binary) 31510780SCurtis.Dunham@arm.com else: 31610780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.membus, self, binary) 3178528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 3188528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 3198287SAli.Saidi@ARM.com 32010747SChris.Emmons@arm.com # This check is for users who have previously put 'android' in 32110747SChris.Emmons@arm.com # the disk image filename to tell the config scripts to 32210747SChris.Emmons@arm.com # prepare the kernel with android-specific boot options. That 32310747SChris.Emmons@arm.com # behavior has been replaced with a more explicit option per 32410747SChris.Emmons@arm.com # the error message below. The disk can have any name now and 32510747SChris.Emmons@arm.com # doesn't need to include 'android' substring. 32610735Srb639@drexel.edu if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 32710747SChris.Emmons@arm.com if 'android' not in mdesc.os_type(): 32810747SChris.Emmons@arm.com fatal("It looks like you are trying to boot an Android " \ 32910747SChris.Emmons@arm.com "platform. To boot Android, you must specify " \ 33010747SChris.Emmons@arm.com "--os-type with an appropriate Android release on " \ 33110747SChris.Emmons@arm.com "the command line.") 33210747SChris.Emmons@arm.com 33310747SChris.Emmons@arm.com # android-specific tweaks 33410747SChris.Emmons@arm.com if 'android' in mdesc.os_type(): 33510747SChris.Emmons@arm.com # generic tweaks 33610747SChris.Emmons@arm.com cmdline += " init=/init" 33710747SChris.Emmons@arm.com 33810747SChris.Emmons@arm.com # release-specific tweaks 33910747SChris.Emmons@arm.com if 'kitkat' in mdesc.os_type(): 34010747SChris.Emmons@arm.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 34110747SChris.Emmons@arm.com "android.bootanim=0" 34210747SChris.Emmons@arm.com 34310594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 34410747SChris.Emmons@arm.com 34510780SCurtis.Dunham@arm.com if external_memory: 34610780SCurtis.Dunham@arm.com # I/O traffic enters iobus 34710780SCurtis.Dunham@arm.com self.external_io = ExternalMaster(port_data="external_io", 34810780SCurtis.Dunham@arm.com port_type=external_memory) 34910780SCurtis.Dunham@arm.com self.external_io.port = self.iobus.slave 35010780SCurtis.Dunham@arm.com 35110780SCurtis.Dunham@arm.com # Ensure iocache only receives traffic destined for (actual) memory. 35210780SCurtis.Dunham@arm.com self.iocache = ExternalSlave(port_data="iocache", 35310780SCurtis.Dunham@arm.com port_type=external_memory, 35410780SCurtis.Dunham@arm.com addr_ranges=self.mem_ranges) 35510780SCurtis.Dunham@arm.com self.iocache.port = self.iobus.master 35610780SCurtis.Dunham@arm.com 35710780SCurtis.Dunham@arm.com # Let system_port get to nvmem and nothing else. 35810780SCurtis.Dunham@arm.com self.bridge.ranges = [self.realview.nvmem.range] 35910780SCurtis.Dunham@arm.com 36010780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.iobus) 36110780SCurtis.Dunham@arm.com else: 36210780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 3637586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 3647586SAli.Saidi@arm.com self.intrctrl = IntrControl() 3657586SAli.Saidi@arm.com self.terminal = Terminal() 3667949SAli.Saidi@ARM.com self.vncserver = VncServer() 3677586SAli.Saidi@arm.com 3688839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3698706Sandreas.hansson@arm.com 3707586SAli.Saidi@arm.com return self 3717586SAli.Saidi@arm.com 3727586SAli.Saidi@arm.com 37310594Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 3745222Sksewell@umich.edu class BaseMalta(Malta): 3755222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3765222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3775222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3785222Sksewell@umich.edu 3795222Sksewell@umich.edu self = LinuxMipsSystem() 3805222Sksewell@umich.edu if not mdesc: 3815222Sksewell@umich.edu # generic system 3825222Sksewell@umich.edu mdesc = SysConfig() 3835222Sksewell@umich.edu self.readfile = mdesc.script() 38410720Sandreas.hansson@arm.com self.iobus = IOXBar() 3859036Sandreas.hansson@arm.com self.membus = MemBus() 3869164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3879826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 3888839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3898839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3905222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3915222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3925222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3935222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3945222Sksewell@umich.edu self.malta = BaseMalta() 3955222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3968839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3978839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3988839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3998839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 4005222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 4015222Sksewell@umich.edu read_only = True)) 4025222Sksewell@umich.edu self.intrctrl = IntrControl() 4035222Sksewell@umich.edu self.mem_mode = mem_mode 4045478Snate@binkert.org self.terminal = Terminal() 4055222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 4065222Sksewell@umich.edu self.console = binary('mips/console') 40710594Sgabeblack@google.com if not cmdline: 40810594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 40910594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 4105222Sksewell@umich.edu 4118839Sandreas.hansson@arm.com self.system_port = self.membus.slave 4128706Sandreas.hansson@arm.com 4135222Sksewell@umich.edu return self 4145222Sksewell@umich.edu 4155323Sgblack@eecs.umich.edudef x86IOAddress(port): 4165357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 4178323Ssteve.reinhardt@amd.com return IO_address_space_base + port 4185323Sgblack@eecs.umich.edu 4198858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 4208713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 4218713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 4228713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 4238713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 4248713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 4258713Sandreas.hansson@arm.com 4269036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 4277905SBrad.Beckmann@amd.com 4287905SBrad.Beckmann@amd.com # North Bridge 42910720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4309164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 4318839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 4328839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 43310438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 43410438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 43510438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 43610438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 43710438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 43810438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 4398713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 4408713Sandreas.hansson@arm.com [ 44110438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 4428713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 4438713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 4448713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 4458713Sandreas.hansson@arm.com Addr.max) 4468713Sandreas.hansson@arm.com ] 4478713Sandreas.hansson@arm.com 4488713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 4498713Sandreas.hansson@arm.com # the local APIC (two pages) 4509164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 4518839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 4528839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 4538815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 4548815Sgblack@eecs.umich.edu interrupts_address_space_base + 4558858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 4568858Sgblack@eecs.umich.edu - 1)] 4577905SBrad.Beckmann@amd.com 4587905SBrad.Beckmann@amd.com # connect the io bus 4597905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 4607905SBrad.Beckmann@amd.com 4618839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 4628706Sandreas.hansson@arm.com 4637905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 4647905SBrad.Beckmann@amd.com # North Bridge 46510720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4667905SBrad.Beckmann@amd.com 4678929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 4688929Snilay@cs.wisc.edu # dma controllers 4698929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 47010118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 4717905SBrad.Beckmann@amd.com 4727905SBrad.Beckmann@amd.com 47310588Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 4745613Sgblack@eecs.umich.edu if self == None: 4755613Sgblack@eecs.umich.edu self = X86System() 4765613Sgblack@eecs.umich.edu 4775133Sgblack@eecs.umich.edu if not mdesc: 4785133Sgblack@eecs.umich.edu # generic system 4795133Sgblack@eecs.umich.edu mdesc = SysConfig() 4805133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4815133Sgblack@eecs.umich.edu 4826802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4836802Sgblack@eecs.umich.edu 4845133Sgblack@eecs.umich.edu # Physical memory 48510041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 48610041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 48710041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 48810041Snilay@cs.wisc.edu excess_mem_size = \ 48910041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 49010041Snilay@cs.wisc.edu if excess_mem_size <= 0: 49110041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 49210041Snilay@cs.wisc.edu else: 49310046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 49410046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 49510046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 49610046Snilay@cs.wisc.edu 49710041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 49810041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4995613Sgblack@eecs.umich.edu 5005613Sgblack@eecs.umich.edu # Platform 5015638Sgblack@eecs.umich.edu self.pc = Pc() 5027905SBrad.Beckmann@amd.com 5037905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 5047905SBrad.Beckmann@amd.com if Ruby: 5057905SBrad.Beckmann@amd.com connectX86RubySystem(self) 5067905SBrad.Beckmann@amd.com else: 5078858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 5085613Sgblack@eecs.umich.edu 5095613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 5105613Sgblack@eecs.umich.edu 5115841Sgblack@eecs.umich.edu # Disks 5125841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 5135841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 5145841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 5155841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 5165841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 5175841Sgblack@eecs.umich.edu 5185615Sgblack@eecs.umich.edu # Add in a Bios information structure. 5195615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 5205615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 5215615Sgblack@eecs.umich.edu 5225641Sgblack@eecs.umich.edu # Set up the Intel MP table 5238323Ssteve.reinhardt@amd.com base_entries = [] 5248323Ssteve.reinhardt@amd.com ext_entries = [] 5256135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 5266135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 5276135Sgblack@eecs.umich.edu local_apic_id = i, 5286135Sgblack@eecs.umich.edu local_apic_version = 0x14, 5296135Sgblack@eecs.umich.edu enable = True, 5306135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 5318323Ssteve.reinhardt@amd.com base_entries.append(bp) 5325644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 5336135Sgblack@eecs.umich.edu id = numCPUs, 5345644Sgblack@eecs.umich.edu version = 0x11, 5355644Sgblack@eecs.umich.edu enable = True, 5365644Sgblack@eecs.umich.edu address = 0xfec00000) 5376135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 5388323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 53910437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 54010437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 54110437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 54210437Smajiuyue@ncic.ac.cn pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') 54310437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 54410437Smajiuyue@ncic.ac.cn isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') 5458323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 54610437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 54710437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 5488323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 5495843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 5505843Sgblack@eecs.umich.edu interrupt_type = 'INT', 5515843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5525843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 55310437Smajiuyue@ncic.ac.cn source_bus_id = 0, 5545843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 5556044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5565843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 5578323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 5586135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 5596135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 5606135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 5616135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5626135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 56310437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5646135Sgblack@eecs.umich.edu source_bus_irq = irq, 5656135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5666135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 5678323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 5686135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 5696135Sgblack@eecs.umich.edu interrupt_type = 'INT', 5706135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5716135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 57210437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5736135Sgblack@eecs.umich.edu source_bus_irq = irq, 5746135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5756135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5768323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5776135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5786135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5796135Sgblack@eecs.umich.edu for i in range(3, 15): 5806135Sgblack@eecs.umich.edu assignISAInt(i, i) 5818323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5828323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5835641Sgblack@eecs.umich.edu 58410594Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 58510594Sgabeblack@google.com cmdline=None): 5865613Sgblack@eecs.umich.edu self = LinuxX86System() 5875613Sgblack@eecs.umich.edu 5887905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5899826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5905613Sgblack@eecs.umich.edu 5915450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5925450Sgblack@eecs.umich.edu # just to avoid corner cases. 5939826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5949232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 59510041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5965450Sgblack@eecs.umich.edu 59710041Snilay@cs.wisc.edu entries = \ 5988323Ssteve.reinhardt@amd.com [ 5998323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 6009622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 6019622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 60210041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 6038323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 60410041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 6059898Sandreas@sandberg.pp.se range_type = 1), 6068323Ssteve.reinhardt@amd.com ] 6075450Sgblack@eecs.umich.edu 60810438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 60910438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 61010438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 61110438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 61210438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 61310438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 61410438Smajiuyue@ncic.ac.cn range_type=2)) 61510438Smajiuyue@ncic.ac.cn 61610438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 61710438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 61810438Smajiuyue@ncic.ac.cn 61910041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 62010041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 62110041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 62210041Snilay@cs.wisc.edu # reserved for devices. 62310041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 62410041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 62510041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 62610041Snilay@cs.wisc.edu 62710041Snilay@cs.wisc.edu self.e820_table.entries = entries 62810041Snilay@cs.wisc.edu 6295330Sgblack@eecs.umich.edu # Command line 63010594Sgabeblack@google.com if not cmdline: 63110594Sgabeblack@google.com cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 63210594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 63310003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 6345133Sgblack@eecs.umich.edu return self 6355133Sgblack@eecs.umich.edu 6363584Ssaidi@eecs.umich.edu 6378801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 6388801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 6392995Ssaidi@eecs.umich.edu self.testsys = testSystem 6402995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 6414981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 6424981Ssaidi@eecs.umich.edu 6438661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 6448661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 6458661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 6468661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 6478661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 6488661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 6498661SAli.Saidi@ARM.com else: 6508661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 6518661SAli.Saidi@ARM.com 6523025Ssaidi@eecs.umich.edu if dumpfile: 6533025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 6543025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 6552934Sktlim@umich.edu 6562934Sktlim@umich.edu return self 65711291Sgabor.dozsa@arm.com 65811291Sgabor.dozsa@arm.com 65911291Sgabor.dozsa@arm.comdef makeDistRoot(testSystem, 66011291Sgabor.dozsa@arm.com rank, 66111291Sgabor.dozsa@arm.com size, 66211291Sgabor.dozsa@arm.com server_name, 66311291Sgabor.dozsa@arm.com server_port, 66411291Sgabor.dozsa@arm.com sync_repeat, 66511291Sgabor.dozsa@arm.com sync_start, 66611291Sgabor.dozsa@arm.com linkspeed, 66711291Sgabor.dozsa@arm.com linkdelay, 66811291Sgabor.dozsa@arm.com dumpfile): 66911291Sgabor.dozsa@arm.com self = Root(full_system = True) 67011291Sgabor.dozsa@arm.com self.testsys = testSystem 67111291Sgabor.dozsa@arm.com 67211291Sgabor.dozsa@arm.com self.etherlink = DistEtherLink(speed = linkspeed, 67311291Sgabor.dozsa@arm.com delay = linkdelay, 67411291Sgabor.dozsa@arm.com dist_rank = rank, 67511291Sgabor.dozsa@arm.com dist_size = size, 67611291Sgabor.dozsa@arm.com server_name = server_name, 67711291Sgabor.dozsa@arm.com server_port = server_port, 67811291Sgabor.dozsa@arm.com sync_start = sync_start, 67911291Sgabor.dozsa@arm.com sync_repeat = sync_repeat) 68011291Sgabor.dozsa@arm.com 68111291Sgabor.dozsa@arm.com if hasattr(testSystem, 'realview'): 68211291Sgabor.dozsa@arm.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 68311291Sgabor.dozsa@arm.com elif hasattr(testSystem, 'tsunami'): 68411291Sgabor.dozsa@arm.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 68511291Sgabor.dozsa@arm.com else: 68611291Sgabor.dozsa@arm.com fatal("Don't know how to connect DistEtherLink to this system") 68711291Sgabor.dozsa@arm.com 68811291Sgabor.dozsa@arm.com if dumpfile: 68911291Sgabor.dozsa@arm.com self.etherdump = EtherDump(file=dumpfile) 69011291Sgabor.dozsa@arm.com self.etherlink.dump = Parent.etherdump 69111291Sgabor.dozsa@arm.com 69211291Sgabor.dozsa@arm.com return self 693