FSConfig.py revision 10697
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 5310405Sandreas.hansson@arm.comclass MemBus(CoherentXBar): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 5810594Sgabeblack@google.comdef fillInCmdline(mdesc, template, **kwargs): 5910594Sgabeblack@google.com kwargs.setdefault('disk', mdesc.disk()) 6010697SCurtis.Dunham@arm.com kwargs.setdefault('rootdev', mdesc.rootdev()) 6110594Sgabeblack@google.com kwargs.setdefault('mem', mdesc.mem()) 6210594Sgabeblack@google.com kwargs.setdefault('script', mdesc.script()) 6310594Sgabeblack@google.com return template % kwargs 6410594Sgabeblack@google.com 6510594Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 6610118Snilay@cs.wisc.edu 674520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 684982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 694520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 704520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 712934Sktlim@umich.edu 722934Sktlim@umich.edu self = LinuxAlphaSystem() 733005Sstever@eecs.umich.edu if not mdesc: 743005Sstever@eecs.umich.edu # generic system 753304Sstever@eecs.umich.edu mdesc = SysConfig() 762995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 7710118Snilay@cs.wisc.edu 7810118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 7910118Snilay@cs.wisc.edu 8010118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 8110405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 8210118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 8310118Snilay@cs.wisc.edu 8410118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 8510118Snilay@cs.wisc.edu self.tsunami.ide.config = self.iobus.master 8610118Snilay@cs.wisc.edu 8710118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 8810118Snilay@cs.wisc.edu self.tsunami.ethernet.config = self.iobus.master 8910118Snilay@cs.wisc.edu 9010118Snilay@cs.wisc.edu if ruby: 9110118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 9210118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 9310118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 9410118Snilay@cs.wisc.edu else: 9510118Snilay@cs.wisc.edu self.membus = MemBus() 9610118Snilay@cs.wisc.edu 9710118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 9810118Snilay@cs.wisc.edu # base address (including the PCI config space) 9910118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 10010118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 1018713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 10210118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 10310118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 10410118Snilay@cs.wisc.edu 10510118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 10610118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 10710118Snilay@cs.wisc.edu 10810118Snilay@cs.wisc.edu self.system_port = self.membus.slave 10910118Snilay@cs.wisc.edu 1109826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1112934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1122934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1132995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1142934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1156765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1166765SBrad.Beckmann@amd.com read_only = True)) 1176765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1186765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1196765SBrad.Beckmann@amd.com self.terminal = Terminal() 1206765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1216765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1226765SBrad.Beckmann@amd.com self.console = binary('console') 12310594Sgabeblack@google.com if not cmdline: 12410594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 12510594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1266765SBrad.Beckmann@amd.com 1276765SBrad.Beckmann@amd.com return self 1286765SBrad.Beckmann@amd.com 12910588Sgabeblack@google.comdef makeSparcSystem(mem_mode, mdesc=None): 1308713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1318713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1328713Sandreas.hansson@arm.com uart_pio_size = 8 1338713Sandreas.hansson@arm.com 1344486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1354486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1364486Sbinkertn@umich.edu read_only=False) 1374486Sbinkertn@umich.edu 1384486Sbinkertn@umich.edu def childImage(self, ci): 1394486Sbinkertn@umich.edu self.image.child.image_file = ci 1404486Sbinkertn@umich.edu 1413584Ssaidi@eecs.umich.edu self = SparcSystem() 1423584Ssaidi@eecs.umich.edu if not mdesc: 1433584Ssaidi@eecs.umich.edu # generic system 1443584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1453584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 14610405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 1479036Sandreas.hansson@arm.com self.membus = MemBus() 1489164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1493743Sgblack@eecs.umich.edu self.t1000 = T1000() 1504104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1513743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1529826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1539826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1548839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1558839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1568839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1578839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1588839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1598839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1603584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1613898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1623898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1638839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1648713Sandreas.hansson@arm.com 1658713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1668713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1678713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1688713Sandreas.hansson@arm.com self.bridge.ranges = \ 1698713Sandreas.hansson@arm.com [ 1708713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1718713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1728713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1738713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1748713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1758713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1768713Sandreas.hansson@arm.com iob_man_addr - 1), 1778713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1788713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1798713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1808713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1818713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1828713Sandreas.hansson@arm.com ] 1834103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1844103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1854103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1863745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1873745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1883745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1893584Ssaidi@eecs.umich.edu 1908839Sandreas.hansson@arm.com self.system_port = self.membus.slave 1918706Sandreas.hansson@arm.com 1923584Ssaidi@eecs.umich.edu return self 1933584Ssaidi@eecs.umich.edu 19410588Sgabeblack@google.comdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 19510594Sgabeblack@google.com dtb_filename=None, bare_metal=False, cmdline=None): 1968061SAli.Saidi@ARM.com assert machine_type 1978061SAli.Saidi@ARM.com 1987586SAli.Saidi@arm.com if bare_metal: 1997586SAli.Saidi@arm.com self = ArmSystem() 2007586SAli.Saidi@arm.com else: 2017586SAli.Saidi@arm.com self = LinuxArmSystem() 2027586SAli.Saidi@arm.com 2037586SAli.Saidi@arm.com if not mdesc: 2047586SAli.Saidi@arm.com # generic system 2057586SAli.Saidi@arm.com mdesc = SysConfig() 2067586SAli.Saidi@arm.com 2077586SAli.Saidi@arm.com self.readfile = mdesc.script() 20810405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 2099036Sandreas.hansson@arm.com self.membus = MemBus() 2107586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2119164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2128839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2138839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2147586SAli.Saidi@arm.com 2157586SAli.Saidi@arm.com self.mem_mode = mem_mode 2167586SAli.Saidi@arm.com 2177586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2187586SAli.Saidi@arm.com self.realview = RealViewPBX() 2197586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2207586SAli.Saidi@arm.com self.realview = RealViewEB() 2218870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2228870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 22310512SAli.Saidi@ARM.com if not dtb_filename: 22410512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus 22510037SARM gem5 Developers elif machine_type == "VExpress_EMM64": 22610037SARM gem5 Developers self.realview = VExpress_EMM64() 22710512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 22810512SAli.Saidi@ARM.com print "Selected 64-bit ARM architecture, updating default disk image..." 22910512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 23010512SAli.Saidi@ARM.com if not dtb_filename: 23110512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch64.20140821.dtb' 2327586SAli.Saidi@arm.com else: 2337586SAli.Saidi@arm.com print "Unknown Machine Type" 2347586SAli.Saidi@arm.com sys.exit(1) 2357586SAli.Saidi@arm.com 2368528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2378528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 23810353SGeoffrey.Blake@arm.com 23910353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 24010353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 2418528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 24210357SAli.Saidi@ARM.com try: 24310357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 24410357SAli.Saidi@ARM.com except: 2458528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2468528SAli.Saidi@ARM.com 24710507SAli.Saidi@ARM.com self.mem_ranges = [] 24810507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 24910507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 25010507SAli.Saidi@ARM.com if size_remain > long(region[1]): 25110507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 25210507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 25310507SAli.Saidi@ARM.com else: 25410507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 25510507SAli.Saidi@ARM.com size_remain = 0 25610507SAli.Saidi@ARM.com break 25710507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 25810507SAli.Saidi@ARM.com " another memory controller for that range.") 25910507SAli.Saidi@ARM.com 26010507SAli.Saidi@ARM.com if size_remain > 0: 26110507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 26210507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 26310507SAli.Saidi@ARM.com " another platform") 26410507SAli.Saidi@ARM.com 2658061SAli.Saidi@ARM.com if bare_metal: 2668061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2678061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2688061SAli.Saidi@ARM.com else: 26910161Satgutier@umich.edu if machine_type == "VExpress_EMM64": 27010512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch64.20140821') 27110161Satgutier@umich.edu elif machine_type == "VExpress_EMM": 27210512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5') 27310161Satgutier@umich.edu else: 27410161Satgutier@umich.edu self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 27510161Satgutier@umich.edu 2769929SAli.Saidi@ARM.com if dtb_filename: 2779929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 2787586SAli.Saidi@arm.com self.machine_type = machine_type 27910071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 28010594Sgabeblack@google.com if not cmdline: 28110594Sgabeblack@google.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 28210594Sgabeblack@google.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 28310697SCurtis.Dunham@arm.com 'mem=%(mem)s root=%(rootdev)s' 28410071Satgutier@umich.edu 2858870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2868528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2878528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2888287SAli.Saidi@ARM.com 2898643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 29010667Smalek.musleh@gmail.com cmdline += " init=/init " 29110594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 2928713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 2937586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2947586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2957586SAli.Saidi@arm.com self.terminal = Terminal() 2967949SAli.Saidi@ARM.com self.vncserver = VncServer() 2977586SAli.Saidi@arm.com 2988839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2998706Sandreas.hansson@arm.com 3007586SAli.Saidi@arm.com return self 3017586SAli.Saidi@arm.com 3027586SAli.Saidi@arm.com 30310594Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 3045222Sksewell@umich.edu class BaseMalta(Malta): 3055222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3065222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3075222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3085222Sksewell@umich.edu 3095222Sksewell@umich.edu self = LinuxMipsSystem() 3105222Sksewell@umich.edu if not mdesc: 3115222Sksewell@umich.edu # generic system 3125222Sksewell@umich.edu mdesc = SysConfig() 3135222Sksewell@umich.edu self.readfile = mdesc.script() 31410405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 3159036Sandreas.hansson@arm.com self.membus = MemBus() 3169164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3179826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 3188839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3198839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3205222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3215222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3225222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3235222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3245222Sksewell@umich.edu self.malta = BaseMalta() 3255222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3268839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3278839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3288839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3298839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3308839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3318839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3325222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3335222Sksewell@umich.edu read_only = True)) 3345222Sksewell@umich.edu self.intrctrl = IntrControl() 3355222Sksewell@umich.edu self.mem_mode = mem_mode 3365478Snate@binkert.org self.terminal = Terminal() 3375222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3385222Sksewell@umich.edu self.console = binary('mips/console') 33910594Sgabeblack@google.com if not cmdline: 34010594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 34110594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 3425222Sksewell@umich.edu 3438839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3448706Sandreas.hansson@arm.com 3455222Sksewell@umich.edu return self 3465222Sksewell@umich.edu 3475323Sgblack@eecs.umich.edudef x86IOAddress(port): 3485357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3498323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3505323Sgblack@eecs.umich.edu 3518858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3528713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3538713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3548713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3558713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3568713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3578713Sandreas.hansson@arm.com 3589036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 3597905SBrad.Beckmann@amd.com 3607905SBrad.Beckmann@amd.com # North Bridge 36110405Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentXBar() 3629164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 3638839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3648839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 36510438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 36610438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 36710438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 36810438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 36910438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 37010438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 3718713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3728713Sandreas.hansson@arm.com [ 37310438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 3748713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3758713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3768713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3778713Sandreas.hansson@arm.com Addr.max) 3788713Sandreas.hansson@arm.com ] 3798713Sandreas.hansson@arm.com 3808713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3818713Sandreas.hansson@arm.com # the local APIC (two pages) 3829164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 3838839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3848839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 3858815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3868815Sgblack@eecs.umich.edu interrupts_address_space_base + 3878858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 3888858Sgblack@eecs.umich.edu - 1)] 3897905SBrad.Beckmann@amd.com 3907905SBrad.Beckmann@amd.com # connect the io bus 3917905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3927905SBrad.Beckmann@amd.com 3938839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 3948706Sandreas.hansson@arm.com 3957905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3967905SBrad.Beckmann@amd.com # North Bridge 39710405Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentXBar() 3987905SBrad.Beckmann@amd.com 3998929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 4008929Snilay@cs.wisc.edu # dma controllers 4018929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 40210118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 4037905SBrad.Beckmann@amd.com 4047905SBrad.Beckmann@amd.com 40510588Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 4065613Sgblack@eecs.umich.edu if self == None: 4075613Sgblack@eecs.umich.edu self = X86System() 4085613Sgblack@eecs.umich.edu 4095133Sgblack@eecs.umich.edu if not mdesc: 4105133Sgblack@eecs.umich.edu # generic system 4115133Sgblack@eecs.umich.edu mdesc = SysConfig() 4125133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4135133Sgblack@eecs.umich.edu 4146802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4156802Sgblack@eecs.umich.edu 4165133Sgblack@eecs.umich.edu # Physical memory 41710041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 41810041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 41910041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 42010041Snilay@cs.wisc.edu excess_mem_size = \ 42110041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 42210041Snilay@cs.wisc.edu if excess_mem_size <= 0: 42310041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 42410041Snilay@cs.wisc.edu else: 42510046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 42610046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 42710046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 42810046Snilay@cs.wisc.edu 42910041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 43010041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4315613Sgblack@eecs.umich.edu 4325613Sgblack@eecs.umich.edu # Platform 4335638Sgblack@eecs.umich.edu self.pc = Pc() 4347905SBrad.Beckmann@amd.com 4357905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4367905SBrad.Beckmann@amd.com if Ruby: 4377905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4387905SBrad.Beckmann@amd.com else: 4398858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4405613Sgblack@eecs.umich.edu 4415613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4425613Sgblack@eecs.umich.edu 4435841Sgblack@eecs.umich.edu # Disks 4445841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4455841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4465841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4475841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4485841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4495841Sgblack@eecs.umich.edu 4505615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4515615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4525615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4535615Sgblack@eecs.umich.edu 4545641Sgblack@eecs.umich.edu # Set up the Intel MP table 4558323Ssteve.reinhardt@amd.com base_entries = [] 4568323Ssteve.reinhardt@amd.com ext_entries = [] 4576135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4586135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4596135Sgblack@eecs.umich.edu local_apic_id = i, 4606135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4616135Sgblack@eecs.umich.edu enable = True, 4626135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4638323Ssteve.reinhardt@amd.com base_entries.append(bp) 4645644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4656135Sgblack@eecs.umich.edu id = numCPUs, 4665644Sgblack@eecs.umich.edu version = 0x11, 4675644Sgblack@eecs.umich.edu enable = True, 4685644Sgblack@eecs.umich.edu address = 0xfec00000) 4696135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4708323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 47110437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 47210437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 47310437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 47410437Smajiuyue@ncic.ac.cn pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') 47510437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 47610437Smajiuyue@ncic.ac.cn isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') 4778323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 47810437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 47910437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 4808323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4815843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4825843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4835843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4845843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 48510437Smajiuyue@ncic.ac.cn source_bus_id = 0, 4865843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4876044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4885843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4898323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4906135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4916135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4926135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4936135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4946135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 49510437Smajiuyue@ncic.ac.cn source_bus_id = 1, 4966135Sgblack@eecs.umich.edu source_bus_irq = irq, 4976135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4986135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4998323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 5006135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 5016135Sgblack@eecs.umich.edu interrupt_type = 'INT', 5026135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5036135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 50410437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5056135Sgblack@eecs.umich.edu source_bus_irq = irq, 5066135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5076135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5088323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5096135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5106135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5116135Sgblack@eecs.umich.edu for i in range(3, 15): 5126135Sgblack@eecs.umich.edu assignISAInt(i, i) 5138323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5148323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5155641Sgblack@eecs.umich.edu 51610594Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 51710594Sgabeblack@google.com cmdline=None): 5185613Sgblack@eecs.umich.edu self = LinuxX86System() 5195613Sgblack@eecs.umich.edu 5207905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5219826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5225613Sgblack@eecs.umich.edu 5235450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5245450Sgblack@eecs.umich.edu # just to avoid corner cases. 5259826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5269232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 52710041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5285450Sgblack@eecs.umich.edu 52910041Snilay@cs.wisc.edu entries = \ 5308323Ssteve.reinhardt@amd.com [ 5318323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5329622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5339622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 53410041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 5358323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 53610041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5379898Sandreas@sandberg.pp.se range_type = 1), 5388323Ssteve.reinhardt@amd.com ] 5395450Sgblack@eecs.umich.edu 54010438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 54110438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 54210438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 54310438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 54410438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 54510438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 54610438Smajiuyue@ncic.ac.cn range_type=2)) 54710438Smajiuyue@ncic.ac.cn 54810438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 54910438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 55010438Smajiuyue@ncic.ac.cn 55110041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 55210041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 55310041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 55410041Snilay@cs.wisc.edu # reserved for devices. 55510041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 55610041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 55710041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 55810041Snilay@cs.wisc.edu 55910041Snilay@cs.wisc.edu self.e820_table.entries = entries 56010041Snilay@cs.wisc.edu 5615330Sgblack@eecs.umich.edu # Command line 56210594Sgabeblack@google.com if not cmdline: 56310594Sgabeblack@google.com cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 56410594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 56510003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 5665133Sgblack@eecs.umich.edu return self 5675133Sgblack@eecs.umich.edu 5683584Ssaidi@eecs.umich.edu 5698801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5708801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5712995Ssaidi@eecs.umich.edu self.testsys = testSystem 5722995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5734981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5744981Ssaidi@eecs.umich.edu 5758661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5768661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5778661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5788661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5798661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5808661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5818661SAli.Saidi@ARM.com else: 5828661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5838661SAli.Saidi@ARM.com 5843025Ssaidi@eecs.umich.edu if dumpfile: 5853025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5863025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5872934Sktlim@umich.edu 5882934Sktlim@umich.edu return self 589