FSConfig.py revision 10594
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 5310405Sandreas.hansson@arm.comclass MemBus(CoherentXBar): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 5810594Sgabeblack@google.comdef fillInCmdline(mdesc, template, **kwargs): 5910594Sgabeblack@google.com kwargs.setdefault('disk', mdesc.disk()) 6010594Sgabeblack@google.com kwargs.setdefault('mem', mdesc.mem()) 6110594Sgabeblack@google.com kwargs.setdefault('script', mdesc.script()) 6210594Sgabeblack@google.com return template % kwargs 6310594Sgabeblack@google.com 6410594Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 6510118Snilay@cs.wisc.edu 664520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 674982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 684520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 694520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 702934Sktlim@umich.edu 712934Sktlim@umich.edu self = LinuxAlphaSystem() 723005Sstever@eecs.umich.edu if not mdesc: 733005Sstever@eecs.umich.edu # generic system 743304Sstever@eecs.umich.edu mdesc = SysConfig() 752995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 7610118Snilay@cs.wisc.edu 7710118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 7810118Snilay@cs.wisc.edu 7910118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 8010405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 8110118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 8210118Snilay@cs.wisc.edu 8310118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 8410118Snilay@cs.wisc.edu self.tsunami.ide.config = self.iobus.master 8510118Snilay@cs.wisc.edu 8610118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 8710118Snilay@cs.wisc.edu self.tsunami.ethernet.config = self.iobus.master 8810118Snilay@cs.wisc.edu 8910118Snilay@cs.wisc.edu if ruby: 9010118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 9110118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 9210118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 9310118Snilay@cs.wisc.edu else: 9410118Snilay@cs.wisc.edu self.membus = MemBus() 9510118Snilay@cs.wisc.edu 9610118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 9710118Snilay@cs.wisc.edu # base address (including the PCI config space) 9810118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 9910118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 1008713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 10110118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 10210118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 10310118Snilay@cs.wisc.edu 10410118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 10510118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 10610118Snilay@cs.wisc.edu 10710118Snilay@cs.wisc.edu self.system_port = self.membus.slave 10810118Snilay@cs.wisc.edu 1099826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1102934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1112934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1122995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1132934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1146765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1156765SBrad.Beckmann@amd.com read_only = True)) 1166765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1176765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1186765SBrad.Beckmann@amd.com self.terminal = Terminal() 1196765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1206765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1216765SBrad.Beckmann@amd.com self.console = binary('console') 12210594Sgabeblack@google.com if not cmdline: 12310594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 12410594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1256765SBrad.Beckmann@amd.com 1266765SBrad.Beckmann@amd.com return self 1276765SBrad.Beckmann@amd.com 12810588Sgabeblack@google.comdef makeSparcSystem(mem_mode, mdesc=None): 1298713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1308713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1318713Sandreas.hansson@arm.com uart_pio_size = 8 1328713Sandreas.hansson@arm.com 1334486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1344486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1354486Sbinkertn@umich.edu read_only=False) 1364486Sbinkertn@umich.edu 1374486Sbinkertn@umich.edu def childImage(self, ci): 1384486Sbinkertn@umich.edu self.image.child.image_file = ci 1394486Sbinkertn@umich.edu 1403584Ssaidi@eecs.umich.edu self = SparcSystem() 1413584Ssaidi@eecs.umich.edu if not mdesc: 1423584Ssaidi@eecs.umich.edu # generic system 1433584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1443584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 14510405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 1469036Sandreas.hansson@arm.com self.membus = MemBus() 1479164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1483743Sgblack@eecs.umich.edu self.t1000 = T1000() 1494104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1503743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1519826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1529826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1538839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1548839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1558839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1568839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1578839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1588839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1593584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1603898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1613898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1628839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1638713Sandreas.hansson@arm.com 1648713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1658713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1668713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1678713Sandreas.hansson@arm.com self.bridge.ranges = \ 1688713Sandreas.hansson@arm.com [ 1698713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1708713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1718713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1728713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1738713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1748713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1758713Sandreas.hansson@arm.com iob_man_addr - 1), 1768713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1778713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1788713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1798713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1808713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1818713Sandreas.hansson@arm.com ] 1824103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1834103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1844103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1853745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1863745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1873745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1883584Ssaidi@eecs.umich.edu 1898839Sandreas.hansson@arm.com self.system_port = self.membus.slave 1908706Sandreas.hansson@arm.com 1913584Ssaidi@eecs.umich.edu return self 1923584Ssaidi@eecs.umich.edu 19310588Sgabeblack@google.comdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 19410594Sgabeblack@google.com dtb_filename=None, bare_metal=False, cmdline=None): 1958061SAli.Saidi@ARM.com assert machine_type 1968061SAli.Saidi@ARM.com 1977586SAli.Saidi@arm.com if bare_metal: 1987586SAli.Saidi@arm.com self = ArmSystem() 1997586SAli.Saidi@arm.com else: 2007586SAli.Saidi@arm.com self = LinuxArmSystem() 2017586SAli.Saidi@arm.com 2027586SAli.Saidi@arm.com if not mdesc: 2037586SAli.Saidi@arm.com # generic system 2047586SAli.Saidi@arm.com mdesc = SysConfig() 2057586SAli.Saidi@arm.com 2067586SAli.Saidi@arm.com self.readfile = mdesc.script() 20710405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 2089036Sandreas.hansson@arm.com self.membus = MemBus() 2097586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2109164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2118839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2128839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2137586SAli.Saidi@arm.com 2147586SAli.Saidi@arm.com self.mem_mode = mem_mode 2157586SAli.Saidi@arm.com 2167586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2177586SAli.Saidi@arm.com self.realview = RealViewPBX() 2187586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2197586SAli.Saidi@arm.com self.realview = RealViewEB() 2208870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2218870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 22210512SAli.Saidi@ARM.com if not dtb_filename: 22310512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus 22410037SARM gem5 Developers elif machine_type == "VExpress_EMM64": 22510037SARM gem5 Developers self.realview = VExpress_EMM64() 22610512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 22710512SAli.Saidi@ARM.com print "Selected 64-bit ARM architecture, updating default disk image..." 22810512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 22910512SAli.Saidi@ARM.com if not dtb_filename: 23010512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch64.20140821.dtb' 2317586SAli.Saidi@arm.com else: 2327586SAli.Saidi@arm.com print "Unknown Machine Type" 2337586SAli.Saidi@arm.com sys.exit(1) 2347586SAli.Saidi@arm.com 2358528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2368528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 23710353SGeoffrey.Blake@arm.com 23810353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 23910353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 2408528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 24110357SAli.Saidi@ARM.com try: 24210357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 24310357SAli.Saidi@ARM.com except: 2448528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2458528SAli.Saidi@ARM.com 24610507SAli.Saidi@ARM.com self.mem_ranges = [] 24710507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 24810507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 24910507SAli.Saidi@ARM.com if size_remain > long(region[1]): 25010507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 25110507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 25210507SAli.Saidi@ARM.com else: 25310507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 25410507SAli.Saidi@ARM.com size_remain = 0 25510507SAli.Saidi@ARM.com break 25610507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 25710507SAli.Saidi@ARM.com " another memory controller for that range.") 25810507SAli.Saidi@ARM.com 25910507SAli.Saidi@ARM.com if size_remain > 0: 26010507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 26110507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 26210507SAli.Saidi@ARM.com " another platform") 26310507SAli.Saidi@ARM.com 2648061SAli.Saidi@ARM.com if bare_metal: 2658061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2668061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2678061SAli.Saidi@ARM.com else: 26810161Satgutier@umich.edu if machine_type == "VExpress_EMM64": 26910512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch64.20140821') 27010161Satgutier@umich.edu elif machine_type == "VExpress_EMM": 27110512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5') 27210161Satgutier@umich.edu else: 27310161Satgutier@umich.edu self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 27410161Satgutier@umich.edu 2759929SAli.Saidi@ARM.com if dtb_filename: 2769929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 2777586SAli.Saidi@arm.com self.machine_type = machine_type 27810071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 27910594Sgabeblack@google.com if not cmdline: 28010594Sgabeblack@google.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 28110594Sgabeblack@google.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 28210594Sgabeblack@google.com 'mem=%(mem)s root=/dev/sda1' 28310071Satgutier@umich.edu 2848870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2858528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2868528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2878287SAli.Saidi@ARM.com 2888643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2898595SAli.Saidi@ARM.com boot_flags += " init=/init " 29010594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 2918713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 2927586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2937586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2947586SAli.Saidi@arm.com self.terminal = Terminal() 2957949SAli.Saidi@ARM.com self.vncserver = VncServer() 2967586SAli.Saidi@arm.com 2978839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2988706Sandreas.hansson@arm.com 2997586SAli.Saidi@arm.com return self 3007586SAli.Saidi@arm.com 3017586SAli.Saidi@arm.com 30210594Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 3035222Sksewell@umich.edu class BaseMalta(Malta): 3045222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3055222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3065222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3075222Sksewell@umich.edu 3085222Sksewell@umich.edu self = LinuxMipsSystem() 3095222Sksewell@umich.edu if not mdesc: 3105222Sksewell@umich.edu # generic system 3115222Sksewell@umich.edu mdesc = SysConfig() 3125222Sksewell@umich.edu self.readfile = mdesc.script() 31310405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 3149036Sandreas.hansson@arm.com self.membus = MemBus() 3159164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3169826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 3178839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3188839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3195222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3205222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3215222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3225222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3235222Sksewell@umich.edu self.malta = BaseMalta() 3245222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3258839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3268839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3278839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3288839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3298839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3308839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3315222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3325222Sksewell@umich.edu read_only = True)) 3335222Sksewell@umich.edu self.intrctrl = IntrControl() 3345222Sksewell@umich.edu self.mem_mode = mem_mode 3355478Snate@binkert.org self.terminal = Terminal() 3365222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3375222Sksewell@umich.edu self.console = binary('mips/console') 33810594Sgabeblack@google.com if not cmdline: 33910594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 34010594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 3415222Sksewell@umich.edu 3428839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3438706Sandreas.hansson@arm.com 3445222Sksewell@umich.edu return self 3455222Sksewell@umich.edu 3465323Sgblack@eecs.umich.edudef x86IOAddress(port): 3475357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3488323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3495323Sgblack@eecs.umich.edu 3508858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3518713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3528713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3538713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3548713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3558713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3568713Sandreas.hansson@arm.com 3579036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 3587905SBrad.Beckmann@amd.com 3597905SBrad.Beckmann@amd.com # North Bridge 36010405Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentXBar() 3619164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 3628839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3638839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 36410438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 36510438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 36610438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 36710438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 36810438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 36910438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 3708713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3718713Sandreas.hansson@arm.com [ 37210438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 3738713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3748713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3758713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3768713Sandreas.hansson@arm.com Addr.max) 3778713Sandreas.hansson@arm.com ] 3788713Sandreas.hansson@arm.com 3798713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3808713Sandreas.hansson@arm.com # the local APIC (two pages) 3819164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 3828839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3838839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 3848815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3858815Sgblack@eecs.umich.edu interrupts_address_space_base + 3868858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 3878858Sgblack@eecs.umich.edu - 1)] 3887905SBrad.Beckmann@amd.com 3897905SBrad.Beckmann@amd.com # connect the io bus 3907905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3917905SBrad.Beckmann@amd.com 3928839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 3938706Sandreas.hansson@arm.com 3947905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3957905SBrad.Beckmann@amd.com # North Bridge 39610405Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentXBar() 3977905SBrad.Beckmann@amd.com 3988929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 3998929Snilay@cs.wisc.edu # dma controllers 4008929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 40110118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 4027905SBrad.Beckmann@amd.com 4037905SBrad.Beckmann@amd.com 40410588Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 4055613Sgblack@eecs.umich.edu if self == None: 4065613Sgblack@eecs.umich.edu self = X86System() 4075613Sgblack@eecs.umich.edu 4085133Sgblack@eecs.umich.edu if not mdesc: 4095133Sgblack@eecs.umich.edu # generic system 4105133Sgblack@eecs.umich.edu mdesc = SysConfig() 4115133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4125133Sgblack@eecs.umich.edu 4136802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4146802Sgblack@eecs.umich.edu 4155133Sgblack@eecs.umich.edu # Physical memory 41610041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 41710041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 41810041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 41910041Snilay@cs.wisc.edu excess_mem_size = \ 42010041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 42110041Snilay@cs.wisc.edu if excess_mem_size <= 0: 42210041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 42310041Snilay@cs.wisc.edu else: 42410046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 42510046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 42610046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 42710046Snilay@cs.wisc.edu 42810041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 42910041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4305613Sgblack@eecs.umich.edu 4315613Sgblack@eecs.umich.edu # Platform 4325638Sgblack@eecs.umich.edu self.pc = Pc() 4337905SBrad.Beckmann@amd.com 4347905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4357905SBrad.Beckmann@amd.com if Ruby: 4367905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4377905SBrad.Beckmann@amd.com else: 4388858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4395613Sgblack@eecs.umich.edu 4405613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4415613Sgblack@eecs.umich.edu 4425841Sgblack@eecs.umich.edu # Disks 4435841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4445841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4455841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4465841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4475841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4485841Sgblack@eecs.umich.edu 4495615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4505615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4515615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4525615Sgblack@eecs.umich.edu 4535641Sgblack@eecs.umich.edu # Set up the Intel MP table 4548323Ssteve.reinhardt@amd.com base_entries = [] 4558323Ssteve.reinhardt@amd.com ext_entries = [] 4566135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4576135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4586135Sgblack@eecs.umich.edu local_apic_id = i, 4596135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4606135Sgblack@eecs.umich.edu enable = True, 4616135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4628323Ssteve.reinhardt@amd.com base_entries.append(bp) 4635644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4646135Sgblack@eecs.umich.edu id = numCPUs, 4655644Sgblack@eecs.umich.edu version = 0x11, 4665644Sgblack@eecs.umich.edu enable = True, 4675644Sgblack@eecs.umich.edu address = 0xfec00000) 4686135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4698323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 47010437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 47110437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 47210437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 47310437Smajiuyue@ncic.ac.cn pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') 47410437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 47510437Smajiuyue@ncic.ac.cn isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') 4768323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 47710437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 47810437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 4798323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4805843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4815843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4825843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4835843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 48410437Smajiuyue@ncic.ac.cn source_bus_id = 0, 4855843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4866044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4875843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4888323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4896135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4906135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4916135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4926135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4936135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 49410437Smajiuyue@ncic.ac.cn source_bus_id = 1, 4956135Sgblack@eecs.umich.edu source_bus_irq = irq, 4966135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4976135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4988323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4996135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 5006135Sgblack@eecs.umich.edu interrupt_type = 'INT', 5016135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5026135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 50310437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5046135Sgblack@eecs.umich.edu source_bus_irq = irq, 5056135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5066135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5078323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5086135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5096135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5106135Sgblack@eecs.umich.edu for i in range(3, 15): 5116135Sgblack@eecs.umich.edu assignISAInt(i, i) 5128323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5138323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5145641Sgblack@eecs.umich.edu 51510594Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 51610594Sgabeblack@google.com cmdline=None): 5175613Sgblack@eecs.umich.edu self = LinuxX86System() 5185613Sgblack@eecs.umich.edu 5197905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5209826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5215613Sgblack@eecs.umich.edu 5225450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5235450Sgblack@eecs.umich.edu # just to avoid corner cases. 5249826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5259232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 52610041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5275450Sgblack@eecs.umich.edu 52810041Snilay@cs.wisc.edu entries = \ 5298323Ssteve.reinhardt@amd.com [ 5308323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5319622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5329622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 53310041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 5348323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 53510041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5369898Sandreas@sandberg.pp.se range_type = 1), 5378323Ssteve.reinhardt@amd.com ] 5385450Sgblack@eecs.umich.edu 53910438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 54010438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 54110438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 54210438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 54310438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 54410438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 54510438Smajiuyue@ncic.ac.cn range_type=2)) 54610438Smajiuyue@ncic.ac.cn 54710438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 54810438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 54910438Smajiuyue@ncic.ac.cn 55010041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 55110041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 55210041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 55310041Snilay@cs.wisc.edu # reserved for devices. 55410041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 55510041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 55610041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 55710041Snilay@cs.wisc.edu 55810041Snilay@cs.wisc.edu self.e820_table.entries = entries 55910041Snilay@cs.wisc.edu 5605330Sgblack@eecs.umich.edu # Command line 56110594Sgabeblack@google.com if not cmdline: 56210594Sgabeblack@google.com cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 56310594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 56410003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 5655133Sgblack@eecs.umich.edu return self 5665133Sgblack@eecs.umich.edu 5673584Ssaidi@eecs.umich.edu 5688801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5698801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5702995Ssaidi@eecs.umich.edu self.testsys = testSystem 5712995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5724981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5734981Ssaidi@eecs.umich.edu 5748661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5758661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5768661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5778661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5788661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5798661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5808661SAli.Saidi@ARM.com else: 5818661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5828661SAli.Saidi@ARM.com 5833025Ssaidi@eecs.umich.edu if dumpfile: 5843025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5853025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5862934Sktlim@umich.edu 5872934Sktlim@umich.edu return self 588