FSConfig.py revision 10512
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 5310405Sandreas.hansson@arm.comclass MemBus(CoherentXBar): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 5810118Snilay@cs.wisc.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False): 5910118Snilay@cs.wisc.edu 604520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 614982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 624520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 634520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 642934Sktlim@umich.edu 652934Sktlim@umich.edu self = LinuxAlphaSystem() 663005Sstever@eecs.umich.edu if not mdesc: 673005Sstever@eecs.umich.edu # generic system 683304Sstever@eecs.umich.edu mdesc = SysConfig() 692995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 7010118Snilay@cs.wisc.edu 7110118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 7210118Snilay@cs.wisc.edu 7310118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 7410405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 7510118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 7610118Snilay@cs.wisc.edu 7710118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 7810118Snilay@cs.wisc.edu self.tsunami.ide.config = self.iobus.master 7910118Snilay@cs.wisc.edu 8010118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 8110118Snilay@cs.wisc.edu self.tsunami.ethernet.config = self.iobus.master 8210118Snilay@cs.wisc.edu 8310118Snilay@cs.wisc.edu if ruby: 8410118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 8510118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 8610118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 8710118Snilay@cs.wisc.edu else: 8810118Snilay@cs.wisc.edu self.membus = MemBus() 8910118Snilay@cs.wisc.edu 9010118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 9110118Snilay@cs.wisc.edu # base address (including the PCI config space) 9210118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 9310118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 948713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 9510118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 9610118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 9710118Snilay@cs.wisc.edu 9810118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 9910118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 10010118Snilay@cs.wisc.edu 10110118Snilay@cs.wisc.edu self.system_port = self.membus.slave 10210118Snilay@cs.wisc.edu 1039826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1042934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1052934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1062995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1072934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1086765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1096765SBrad.Beckmann@amd.com read_only = True)) 1106765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1116765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1126765SBrad.Beckmann@amd.com self.terminal = Terminal() 1136765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1146765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1156765SBrad.Beckmann@amd.com self.console = binary('console') 1166765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1176765SBrad.Beckmann@amd.com 1186765SBrad.Beckmann@amd.com return self 1196765SBrad.Beckmann@amd.com 1209826Sandreas.hansson@arm.comdef makeSparcSystem(mem_mode, mdesc = None): 1218713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1228713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1238713Sandreas.hansson@arm.com uart_pio_size = 8 1248713Sandreas.hansson@arm.com 1254486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1264486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1274486Sbinkertn@umich.edu read_only=False) 1284486Sbinkertn@umich.edu 1294486Sbinkertn@umich.edu def childImage(self, ci): 1304486Sbinkertn@umich.edu self.image.child.image_file = ci 1314486Sbinkertn@umich.edu 1323584Ssaidi@eecs.umich.edu self = SparcSystem() 1333584Ssaidi@eecs.umich.edu if not mdesc: 1343584Ssaidi@eecs.umich.edu # generic system 1353584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1363584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 13710405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 1389036Sandreas.hansson@arm.com self.membus = MemBus() 1399164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1403743Sgblack@eecs.umich.edu self.t1000 = T1000() 1414104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1423743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1439826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1449826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1458839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1468839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1478839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1488839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1498839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1508839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1513584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1523898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1533898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1548839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1558713Sandreas.hansson@arm.com 1568713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1578713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1588713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1598713Sandreas.hansson@arm.com self.bridge.ranges = \ 1608713Sandreas.hansson@arm.com [ 1618713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1628713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1638713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1648713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1658713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1668713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1678713Sandreas.hansson@arm.com iob_man_addr - 1), 1688713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1698713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1708713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1718713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1728713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1738713Sandreas.hansson@arm.com ] 1744103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1754103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1764103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1773745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1783745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1793745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1803584Ssaidi@eecs.umich.edu 1818839Sandreas.hansson@arm.com self.system_port = self.membus.slave 1828706Sandreas.hansson@arm.com 1833584Ssaidi@eecs.umich.edu return self 1843584Ssaidi@eecs.umich.edu 18510512SAli.Saidi@ARM.comdef makeArmSystem(mem_mode, machine_type, num_cpus = 1, mdesc = None, 1869665Sandreas.hansson@arm.com dtb_filename = None, bare_metal=False): 1878061SAli.Saidi@ARM.com assert machine_type 1888061SAli.Saidi@ARM.com 1897586SAli.Saidi@arm.com if bare_metal: 1907586SAli.Saidi@arm.com self = ArmSystem() 1917586SAli.Saidi@arm.com else: 1927586SAli.Saidi@arm.com self = LinuxArmSystem() 1937586SAli.Saidi@arm.com 1947586SAli.Saidi@arm.com if not mdesc: 1957586SAli.Saidi@arm.com # generic system 1967586SAli.Saidi@arm.com mdesc = SysConfig() 1977586SAli.Saidi@arm.com 1987586SAli.Saidi@arm.com self.readfile = mdesc.script() 19910405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 2009036Sandreas.hansson@arm.com self.membus = MemBus() 2017586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2029164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2038839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2048839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2057586SAli.Saidi@arm.com 2067586SAli.Saidi@arm.com self.mem_mode = mem_mode 2077586SAli.Saidi@arm.com 2087586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2097586SAli.Saidi@arm.com self.realview = RealViewPBX() 2107586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2117586SAli.Saidi@arm.com self.realview = RealViewEB() 2128870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2138870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 21410512SAli.Saidi@ARM.com if not dtb_filename: 21510512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus 21610037SARM gem5 Developers elif machine_type == "VExpress_EMM64": 21710037SARM gem5 Developers self.realview = VExpress_EMM64() 21810512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 21910512SAli.Saidi@ARM.com print "Selected 64-bit ARM architecture, updating default disk image..." 22010512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 22110512SAli.Saidi@ARM.com if not dtb_filename: 22210512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch64.20140821.dtb' 2237586SAli.Saidi@arm.com else: 2247586SAli.Saidi@arm.com print "Unknown Machine Type" 2257586SAli.Saidi@arm.com sys.exit(1) 2267586SAli.Saidi@arm.com 2278528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2288528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 22910353SGeoffrey.Blake@arm.com 23010353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 23110353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 2328528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 23310357SAli.Saidi@ARM.com try: 23410357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 23510357SAli.Saidi@ARM.com except: 2368528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2378528SAli.Saidi@ARM.com 23810507SAli.Saidi@ARM.com self.mem_ranges = [] 23910507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 24010507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 24110507SAli.Saidi@ARM.com if size_remain > long(region[1]): 24210507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 24310507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 24410507SAli.Saidi@ARM.com else: 24510507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 24610507SAli.Saidi@ARM.com size_remain = 0 24710507SAli.Saidi@ARM.com break 24810507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 24910507SAli.Saidi@ARM.com " another memory controller for that range.") 25010507SAli.Saidi@ARM.com 25110507SAli.Saidi@ARM.com if size_remain > 0: 25210507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 25310507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 25410507SAli.Saidi@ARM.com " another platform") 25510507SAli.Saidi@ARM.com 2568061SAli.Saidi@ARM.com if bare_metal: 2578061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2588061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2598061SAli.Saidi@ARM.com else: 26010161Satgutier@umich.edu if machine_type == "VExpress_EMM64": 26110512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch64.20140821') 26210161Satgutier@umich.edu elif machine_type == "VExpress_EMM": 26310512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5') 26410161Satgutier@umich.edu else: 26510161Satgutier@umich.edu self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 26610161Satgutier@umich.edu 2679929SAli.Saidi@ARM.com if dtb_filename: 2689929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 2697586SAli.Saidi@arm.com self.machine_type = machine_type 27010071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 27110071Satgutier@umich.edu boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 27210071Satgutier@umich.edu 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 27310071Satgutier@umich.edu 'mem=%s root=/dev/sda1' % mdesc.mem() 27410071Satgutier@umich.edu 2758870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2768528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2778528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2788287SAli.Saidi@ARM.com 2798643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2808595SAli.Saidi@ARM.com boot_flags += " init=/init " 2818212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 2828713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 2837586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2847586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2857586SAli.Saidi@arm.com self.terminal = Terminal() 2867949SAli.Saidi@ARM.com self.vncserver = VncServer() 2877586SAli.Saidi@arm.com 2888839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2898706Sandreas.hansson@arm.com 2907586SAli.Saidi@arm.com return self 2917586SAli.Saidi@arm.com 2927586SAli.Saidi@arm.com 2939826Sandreas.hansson@arm.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 2945222Sksewell@umich.edu class BaseMalta(Malta): 2955222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 2965222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 2975222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 2985222Sksewell@umich.edu 2995222Sksewell@umich.edu self = LinuxMipsSystem() 3005222Sksewell@umich.edu if not mdesc: 3015222Sksewell@umich.edu # generic system 3025222Sksewell@umich.edu mdesc = SysConfig() 3035222Sksewell@umich.edu self.readfile = mdesc.script() 30410405Sandreas.hansson@arm.com self.iobus = NoncoherentXBar() 3059036Sandreas.hansson@arm.com self.membus = MemBus() 3069164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3079826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 3088839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3098839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3105222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3115222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3125222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3135222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3145222Sksewell@umich.edu self.malta = BaseMalta() 3155222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3168839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3178839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3188839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3198839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3208839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3218839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3225222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3235222Sksewell@umich.edu read_only = True)) 3245222Sksewell@umich.edu self.intrctrl = IntrControl() 3255222Sksewell@umich.edu self.mem_mode = mem_mode 3265478Snate@binkert.org self.terminal = Terminal() 3275222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3285222Sksewell@umich.edu self.console = binary('mips/console') 3295222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3305222Sksewell@umich.edu 3318839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3328706Sandreas.hansson@arm.com 3335222Sksewell@umich.edu return self 3345222Sksewell@umich.edu 3355323Sgblack@eecs.umich.edudef x86IOAddress(port): 3365357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3378323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3385323Sgblack@eecs.umich.edu 3398858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3408713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3418713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3428713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3438713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3448713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3458713Sandreas.hansson@arm.com 3469036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 3477905SBrad.Beckmann@amd.com 3487905SBrad.Beckmann@amd.com # North Bridge 34910405Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentXBar() 3509164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 3518839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3528839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 35310438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 35410438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 35510438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 35610438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 35710438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 35810438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 3598713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3608713Sandreas.hansson@arm.com [ 36110438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 3628713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3638713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3648713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3658713Sandreas.hansson@arm.com Addr.max) 3668713Sandreas.hansson@arm.com ] 3678713Sandreas.hansson@arm.com 3688713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3698713Sandreas.hansson@arm.com # the local APIC (two pages) 3709164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 3718839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3728839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 3738815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3748815Sgblack@eecs.umich.edu interrupts_address_space_base + 3758858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 3768858Sgblack@eecs.umich.edu - 1)] 3777905SBrad.Beckmann@amd.com 3787905SBrad.Beckmann@amd.com # connect the io bus 3797905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3807905SBrad.Beckmann@amd.com 3818839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 3828706Sandreas.hansson@arm.com 3837905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3847905SBrad.Beckmann@amd.com # North Bridge 38510405Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentXBar() 3867905SBrad.Beckmann@amd.com 3878929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 3888929Snilay@cs.wisc.edu # dma controllers 3898929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 39010118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 3917905SBrad.Beckmann@amd.com 3927905SBrad.Beckmann@amd.com 3939826Sandreas.hansson@arm.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, 3949665Sandreas.hansson@arm.com Ruby = False): 3955613Sgblack@eecs.umich.edu if self == None: 3965613Sgblack@eecs.umich.edu self = X86System() 3975613Sgblack@eecs.umich.edu 3985133Sgblack@eecs.umich.edu if not mdesc: 3995133Sgblack@eecs.umich.edu # generic system 4005133Sgblack@eecs.umich.edu mdesc = SysConfig() 4015133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4025133Sgblack@eecs.umich.edu 4036802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4046802Sgblack@eecs.umich.edu 4055133Sgblack@eecs.umich.edu # Physical memory 40610041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 40710041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 40810041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 40910041Snilay@cs.wisc.edu excess_mem_size = \ 41010041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 41110041Snilay@cs.wisc.edu if excess_mem_size <= 0: 41210041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 41310041Snilay@cs.wisc.edu else: 41410046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 41510046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 41610046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 41710046Snilay@cs.wisc.edu 41810041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 41910041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4205613Sgblack@eecs.umich.edu 4215613Sgblack@eecs.umich.edu # Platform 4225638Sgblack@eecs.umich.edu self.pc = Pc() 4237905SBrad.Beckmann@amd.com 4247905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4257905SBrad.Beckmann@amd.com if Ruby: 4267905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4277905SBrad.Beckmann@amd.com else: 4288858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4295613Sgblack@eecs.umich.edu 4305613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4315613Sgblack@eecs.umich.edu 4325841Sgblack@eecs.umich.edu # Disks 4335841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4345841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4355841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4365841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4375841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4385841Sgblack@eecs.umich.edu 4395615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4405615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4415615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4425615Sgblack@eecs.umich.edu 4435641Sgblack@eecs.umich.edu # Set up the Intel MP table 4448323Ssteve.reinhardt@amd.com base_entries = [] 4458323Ssteve.reinhardt@amd.com ext_entries = [] 4466135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4476135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4486135Sgblack@eecs.umich.edu local_apic_id = i, 4496135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4506135Sgblack@eecs.umich.edu enable = True, 4516135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4528323Ssteve.reinhardt@amd.com base_entries.append(bp) 4535644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4546135Sgblack@eecs.umich.edu id = numCPUs, 4555644Sgblack@eecs.umich.edu version = 0x11, 4565644Sgblack@eecs.umich.edu enable = True, 4575644Sgblack@eecs.umich.edu address = 0xfec00000) 4586135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4598323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 46010437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 46110437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 46210437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 46310437Smajiuyue@ncic.ac.cn pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') 46410437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 46510437Smajiuyue@ncic.ac.cn isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') 4668323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 46710437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 46810437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 4698323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4705843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4715843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4725843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4735843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 47410437Smajiuyue@ncic.ac.cn source_bus_id = 0, 4755843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4766044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4775843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4788323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4796135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4806135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4816135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4826135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4836135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 48410437Smajiuyue@ncic.ac.cn source_bus_id = 1, 4856135Sgblack@eecs.umich.edu source_bus_irq = irq, 4866135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4876135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4888323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4896135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4906135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4916135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4926135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 49310437Smajiuyue@ncic.ac.cn source_bus_id = 1, 4946135Sgblack@eecs.umich.edu source_bus_irq = irq, 4956135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4966135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 4978323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 4986135Sgblack@eecs.umich.edu assignISAInt(0, 2) 4996135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5006135Sgblack@eecs.umich.edu for i in range(3, 15): 5016135Sgblack@eecs.umich.edu assignISAInt(i, i) 5028323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5038323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5045641Sgblack@eecs.umich.edu 5059826Sandreas.hansson@arm.comdef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, 5069665Sandreas.hansson@arm.com Ruby = False): 5075613Sgblack@eecs.umich.edu self = LinuxX86System() 5085613Sgblack@eecs.umich.edu 5097905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5109826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5115613Sgblack@eecs.umich.edu 5125450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5135450Sgblack@eecs.umich.edu # just to avoid corner cases. 5149826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5159232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 51610041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5175450Sgblack@eecs.umich.edu 51810041Snilay@cs.wisc.edu entries = \ 5198323Ssteve.reinhardt@amd.com [ 5208323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5219622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5229622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 52310041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 5248323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 52510041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5269898Sandreas@sandberg.pp.se range_type = 1), 5278323Ssteve.reinhardt@amd.com ] 5285450Sgblack@eecs.umich.edu 52910438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 53010438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 53110438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 53210438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 53310438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 53410438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 53510438Smajiuyue@ncic.ac.cn range_type=2)) 53610438Smajiuyue@ncic.ac.cn 53710438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 53810438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 53910438Smajiuyue@ncic.ac.cn 54010041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 54110041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 54210041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 54310041Snilay@cs.wisc.edu # reserved for devices. 54410041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 54510041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 54610041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 54710041Snilay@cs.wisc.edu 54810041Snilay@cs.wisc.edu self.e820_table.entries = entries 54910041Snilay@cs.wisc.edu 5505330Sgblack@eecs.umich.edu # Command line 5515847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5525845Sgblack@eecs.umich.edu 'root=/dev/hda1' 55310003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 5545133Sgblack@eecs.umich.edu return self 5555133Sgblack@eecs.umich.edu 5563584Ssaidi@eecs.umich.edu 5578801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5588801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5592995Ssaidi@eecs.umich.edu self.testsys = testSystem 5602995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5614981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5624981Ssaidi@eecs.umich.edu 5638661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5648661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5658661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5668661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5678661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5688661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5698661SAli.Saidi@ARM.com else: 5708661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5718661SAli.Saidi@ARM.com 5723025Ssaidi@eecs.umich.edu if dumpfile: 5733025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5743025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5752934Sktlim@umich.edu 5762934Sktlim@umich.edu return self 577