FSConfig.py revision 10353
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 539036Sandreas.hansson@arm.comclass MemBus(CoherentBus): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 5810118Snilay@cs.wisc.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False): 5910118Snilay@cs.wisc.edu 604520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 614982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 624520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 634520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 642934Sktlim@umich.edu 652934Sktlim@umich.edu self = LinuxAlphaSystem() 663005Sstever@eecs.umich.edu if not mdesc: 673005Sstever@eecs.umich.edu # generic system 683304Sstever@eecs.umich.edu mdesc = SysConfig() 692995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 7010118Snilay@cs.wisc.edu 7110118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 7210118Snilay@cs.wisc.edu 7310118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 749036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 7510118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 7610118Snilay@cs.wisc.edu 7710118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 7810118Snilay@cs.wisc.edu self.tsunami.ide.config = self.iobus.master 7910118Snilay@cs.wisc.edu 8010118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 8110118Snilay@cs.wisc.edu self.tsunami.ethernet.config = self.iobus.master 8210118Snilay@cs.wisc.edu 8310118Snilay@cs.wisc.edu if ruby: 8410118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 8510118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 8610118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 8710118Snilay@cs.wisc.edu else: 8810118Snilay@cs.wisc.edu self.membus = MemBus() 8910118Snilay@cs.wisc.edu 9010118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 9110118Snilay@cs.wisc.edu # base address (including the PCI config space) 9210118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 9310118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 948713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 9510118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 9610118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 9710118Snilay@cs.wisc.edu 9810118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 9910118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 10010118Snilay@cs.wisc.edu 10110118Snilay@cs.wisc.edu self.system_port = self.membus.slave 10210118Snilay@cs.wisc.edu 1039826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1042934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1052934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1062995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1072934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1086765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1096765SBrad.Beckmann@amd.com read_only = True)) 1106765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1116765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1126765SBrad.Beckmann@amd.com self.terminal = Terminal() 1136765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1146765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1156765SBrad.Beckmann@amd.com self.console = binary('console') 1166765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1176765SBrad.Beckmann@amd.com 1186765SBrad.Beckmann@amd.com return self 1196765SBrad.Beckmann@amd.com 1209826Sandreas.hansson@arm.comdef makeSparcSystem(mem_mode, mdesc = None): 1218713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1228713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1238713Sandreas.hansson@arm.com uart_pio_size = 8 1248713Sandreas.hansson@arm.com 1254486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1264486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1274486Sbinkertn@umich.edu read_only=False) 1284486Sbinkertn@umich.edu 1294486Sbinkertn@umich.edu def childImage(self, ci): 1304486Sbinkertn@umich.edu self.image.child.image_file = ci 1314486Sbinkertn@umich.edu 1323584Ssaidi@eecs.umich.edu self = SparcSystem() 1333584Ssaidi@eecs.umich.edu if not mdesc: 1343584Ssaidi@eecs.umich.edu # generic system 1353584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1363584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1379036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 1389036Sandreas.hansson@arm.com self.membus = MemBus() 1399164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1403743Sgblack@eecs.umich.edu self.t1000 = T1000() 1414104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1423743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1439826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1449826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1458839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1468839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1478839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1488839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1498839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1508839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1513584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1523898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1533898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1548839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1558713Sandreas.hansson@arm.com 1568713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1578713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1588713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1598713Sandreas.hansson@arm.com self.bridge.ranges = \ 1608713Sandreas.hansson@arm.com [ 1618713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1628713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1638713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1648713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1658713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1668713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1678713Sandreas.hansson@arm.com iob_man_addr - 1), 1688713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1698713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1708713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1718713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1728713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1738713Sandreas.hansson@arm.com ] 1744103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1754103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1764103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1773745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1783745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1793745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1803584Ssaidi@eecs.umich.edu 1818839Sandreas.hansson@arm.com self.system_port = self.membus.slave 1828706Sandreas.hansson@arm.com 1833584Ssaidi@eecs.umich.edu return self 1843584Ssaidi@eecs.umich.edu 1859826Sandreas.hansson@arm.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, 1869665Sandreas.hansson@arm.com dtb_filename = None, bare_metal=False): 1878061SAli.Saidi@ARM.com assert machine_type 1888061SAli.Saidi@ARM.com 1897586SAli.Saidi@arm.com if bare_metal: 1907586SAli.Saidi@arm.com self = ArmSystem() 1917586SAli.Saidi@arm.com else: 1927586SAli.Saidi@arm.com self = LinuxArmSystem() 1937586SAli.Saidi@arm.com 1947586SAli.Saidi@arm.com if not mdesc: 1957586SAli.Saidi@arm.com # generic system 1967586SAli.Saidi@arm.com mdesc = SysConfig() 1977586SAli.Saidi@arm.com 1987586SAli.Saidi@arm.com self.readfile = mdesc.script() 1999036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 2009036Sandreas.hansson@arm.com self.membus = MemBus() 2017586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2029164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2038839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2048839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2057586SAli.Saidi@arm.com 2067586SAli.Saidi@arm.com self.mem_mode = mem_mode 2077586SAli.Saidi@arm.com 2087586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2097586SAli.Saidi@arm.com self.realview = RealViewPBX() 2107586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2117586SAli.Saidi@arm.com self.realview = RealViewEB() 2128525SAli.Saidi@ARM.com elif machine_type == "VExpress_ELT": 2138525SAli.Saidi@ARM.com self.realview = VExpress_ELT() 2148870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2158870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 21610037SARM gem5 Developers elif machine_type == "VExpress_EMM64": 21710037SARM gem5 Developers self.realview = VExpress_EMM64() 2187586SAli.Saidi@arm.com else: 2197586SAli.Saidi@arm.com print "Unknown Machine Type" 2207586SAli.Saidi@arm.com sys.exit(1) 2217586SAli.Saidi@arm.com 2228528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2238528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 22410353SGeoffrey.Blake@arm.com 22510353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 22610353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 2278528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 22810071Satgutier@umich.edu # assuming we've got one; EMM64 is an exception for the moment 22910071Satgutier@umich.edu if machine_type != "VExpress_EMM64": 23010071Satgutier@umich.edu try: 23110071Satgutier@umich.edu self.realview.ide.disks = [self.cf0] 23210071Satgutier@umich.edu except: 23310071Satgutier@umich.edu self.realview.cf_ctrl.disks = [self.cf0] 23410071Satgutier@umich.edu else: 2358528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2368528SAli.Saidi@ARM.com 2378061SAli.Saidi@ARM.com if bare_metal: 2388061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2398061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2409845SAli.Saidi@ARM.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 2419845SAli.Saidi@ARM.com size = mdesc.mem())] 2428061SAli.Saidi@ARM.com else: 24310161Satgutier@umich.edu if machine_type == "VExpress_EMM64": 24410161Satgutier@umich.edu self.kernel = binary('vmlinux-3.14-aarch64-vexpress-emm64') 24510161Satgutier@umich.edu elif machine_type == "VExpress_EMM": 24610161Satgutier@umich.edu self.kernel = binary('vmlinux-3.3-arm-vexpress-emm-pcie') 24710161Satgutier@umich.edu else: 24810161Satgutier@umich.edu self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 24910161Satgutier@umich.edu 2509929SAli.Saidi@ARM.com if dtb_filename: 2519929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 2527586SAli.Saidi@arm.com self.machine_type = machine_type 2538894Ssaidi@eecs.umich.edu if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2548870SAli.Saidi@ARM.com print "The currently selected ARM platforms doesn't support" 2558870SAli.Saidi@ARM.com print " the amount of DRAM you've selected. Please try" 2568870SAli.Saidi@ARM.com print " another platform" 2578894Ssaidi@eecs.umich.edu sys.exit(1) 2588528SAli.Saidi@ARM.com 25910071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 26010071Satgutier@umich.edu boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 26110071Satgutier@umich.edu 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 26210071Satgutier@umich.edu 'mem=%s root=/dev/sda1' % mdesc.mem() 26310071Satgutier@umich.edu 2649826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 2659826Sandreas.hansson@arm.com size = mdesc.mem())] 2668870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2678528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2688528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2698287SAli.Saidi@ARM.com 2708643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2718595SAli.Saidi@ARM.com boot_flags += " init=/init " 2728212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 2738713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 2747586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2757586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2767586SAli.Saidi@arm.com self.terminal = Terminal() 2777949SAli.Saidi@ARM.com self.vncserver = VncServer() 2787586SAli.Saidi@arm.com 2798839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2808706Sandreas.hansson@arm.com 2817586SAli.Saidi@arm.com return self 2827586SAli.Saidi@arm.com 2837586SAli.Saidi@arm.com 2849826Sandreas.hansson@arm.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 2855222Sksewell@umich.edu class BaseMalta(Malta): 2865222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 2875222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 2885222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 2895222Sksewell@umich.edu 2905222Sksewell@umich.edu self = LinuxMipsSystem() 2915222Sksewell@umich.edu if not mdesc: 2925222Sksewell@umich.edu # generic system 2935222Sksewell@umich.edu mdesc = SysConfig() 2945222Sksewell@umich.edu self.readfile = mdesc.script() 2959036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 2969036Sandreas.hansson@arm.com self.membus = MemBus() 2979164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2989826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 2998839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3008839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3015222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3025222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3035222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3045222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3055222Sksewell@umich.edu self.malta = BaseMalta() 3065222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3078839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3088839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3098839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3108839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3118839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3128839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3135222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3145222Sksewell@umich.edu read_only = True)) 3155222Sksewell@umich.edu self.intrctrl = IntrControl() 3165222Sksewell@umich.edu self.mem_mode = mem_mode 3175478Snate@binkert.org self.terminal = Terminal() 3185222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3195222Sksewell@umich.edu self.console = binary('mips/console') 3205222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3215222Sksewell@umich.edu 3228839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3238706Sandreas.hansson@arm.com 3245222Sksewell@umich.edu return self 3255222Sksewell@umich.edu 3265323Sgblack@eecs.umich.edudef x86IOAddress(port): 3275357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3288323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3295323Sgblack@eecs.umich.edu 3308858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3318713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3328713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3338713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3348713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3358713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3368713Sandreas.hansson@arm.com 3379036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 3387905SBrad.Beckmann@amd.com 3397905SBrad.Beckmann@amd.com # North Bridge 3409036Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentBus() 3419164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 3428839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3438839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 3448713Sandreas.hansson@arm.com # Allow the bridge to pass through the IO APIC (two pages), 3458713Sandreas.hansson@arm.com # everything in the IO address range up to the local APIC, and 3468713Sandreas.hansson@arm.com # then the entire PCI address space and beyond 3478713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3488713Sandreas.hansson@arm.com [ 3498713Sandreas.hansson@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3508713Sandreas.hansson@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 3518713Sandreas.hansson@arm.com APIC_range_size - 1), 3528713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3538713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3548713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3558713Sandreas.hansson@arm.com Addr.max) 3568713Sandreas.hansson@arm.com ] 3578713Sandreas.hansson@arm.com 3588713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3598713Sandreas.hansson@arm.com # the local APIC (two pages) 3609164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 3618839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3628839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 3638815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3648815Sgblack@eecs.umich.edu interrupts_address_space_base + 3658858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 3668858Sgblack@eecs.umich.edu - 1)] 3677905SBrad.Beckmann@amd.com 3687905SBrad.Beckmann@amd.com # connect the io bus 3697905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3707905SBrad.Beckmann@amd.com 3718839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 3728706Sandreas.hansson@arm.com 3737905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3747905SBrad.Beckmann@amd.com # North Bridge 37510118Snilay@cs.wisc.edu x86_sys.iobus = NoncoherentBus() 3767905SBrad.Beckmann@amd.com 3778929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 3788929Snilay@cs.wisc.edu # dma controllers 3798929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 38010118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 3817905SBrad.Beckmann@amd.com 3827905SBrad.Beckmann@amd.com 3839826Sandreas.hansson@arm.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, 3849665Sandreas.hansson@arm.com Ruby = False): 3855613Sgblack@eecs.umich.edu if self == None: 3865613Sgblack@eecs.umich.edu self = X86System() 3875613Sgblack@eecs.umich.edu 3885133Sgblack@eecs.umich.edu if not mdesc: 3895133Sgblack@eecs.umich.edu # generic system 3905133Sgblack@eecs.umich.edu mdesc = SysConfig() 3915133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 3925133Sgblack@eecs.umich.edu 3936802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 3946802Sgblack@eecs.umich.edu 3955133Sgblack@eecs.umich.edu # Physical memory 39610041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 39710041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 39810041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 39910041Snilay@cs.wisc.edu excess_mem_size = \ 40010041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 40110041Snilay@cs.wisc.edu if excess_mem_size <= 0: 40210041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 40310041Snilay@cs.wisc.edu else: 40410046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 40510046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 40610046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 40710046Snilay@cs.wisc.edu 40810041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 40910041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4105613Sgblack@eecs.umich.edu 4115613Sgblack@eecs.umich.edu # Platform 4125638Sgblack@eecs.umich.edu self.pc = Pc() 4137905SBrad.Beckmann@amd.com 4147905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4157905SBrad.Beckmann@amd.com if Ruby: 4167905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4177905SBrad.Beckmann@amd.com else: 4188858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4195613Sgblack@eecs.umich.edu 4205613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4215613Sgblack@eecs.umich.edu 4225841Sgblack@eecs.umich.edu # Disks 4235841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4245841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4255841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4265841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4275841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4285841Sgblack@eecs.umich.edu 4295615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4305615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4315615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4325615Sgblack@eecs.umich.edu 4335641Sgblack@eecs.umich.edu # Set up the Intel MP table 4348323Ssteve.reinhardt@amd.com base_entries = [] 4358323Ssteve.reinhardt@amd.com ext_entries = [] 4366135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4376135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4386135Sgblack@eecs.umich.edu local_apic_id = i, 4396135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4406135Sgblack@eecs.umich.edu enable = True, 4416135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4428323Ssteve.reinhardt@amd.com base_entries.append(bp) 4435644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4446135Sgblack@eecs.umich.edu id = numCPUs, 4455644Sgblack@eecs.umich.edu version = 0x11, 4465644Sgblack@eecs.umich.edu enable = True, 4475644Sgblack@eecs.umich.edu address = 0xfec00000) 4486135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4498323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 4505644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4518323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 4525843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4538323Ssteve.reinhardt@amd.com base_entries.append(pci_bus) 4545843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4555843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4568323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4575843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4585843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4595843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4605843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4615843Sgblack@eecs.umich.edu source_bus_id = 1, 4625843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4636044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4645843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4658323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4666135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4676135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4686135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4696135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4706135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4716135Sgblack@eecs.umich.edu source_bus_id = 0, 4726135Sgblack@eecs.umich.edu source_bus_irq = irq, 4736135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4746135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4758323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4766135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4776135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4786135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4796135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4806135Sgblack@eecs.umich.edu source_bus_id = 0, 4816135Sgblack@eecs.umich.edu source_bus_irq = irq, 4826135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4836135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 4848323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 4856135Sgblack@eecs.umich.edu assignISAInt(0, 2) 4866135Sgblack@eecs.umich.edu assignISAInt(1, 1) 4876135Sgblack@eecs.umich.edu for i in range(3, 15): 4886135Sgblack@eecs.umich.edu assignISAInt(i, i) 4898323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 4908323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 4915641Sgblack@eecs.umich.edu 4929826Sandreas.hansson@arm.comdef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, 4939665Sandreas.hansson@arm.com Ruby = False): 4945613Sgblack@eecs.umich.edu self = LinuxX86System() 4955613Sgblack@eecs.umich.edu 4967905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 4979826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 4985613Sgblack@eecs.umich.edu 4995450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5005450Sgblack@eecs.umich.edu # just to avoid corner cases. 5019826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5029232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 50310041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5045450Sgblack@eecs.umich.edu 50510041Snilay@cs.wisc.edu entries = \ 5068323Ssteve.reinhardt@amd.com [ 5078323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5089622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5099622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 51010041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 5118323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 51210041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5139898Sandreas@sandberg.pp.se range_type = 1), 5149898Sandreas@sandberg.pp.se # Reserve the last 16kB of the 32-bit address space for the 5159898Sandreas@sandberg.pp.se # m5op interface 5169898Sandreas@sandberg.pp.se X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2), 5178323Ssteve.reinhardt@amd.com ] 5185450Sgblack@eecs.umich.edu 51910041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 52010041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 52110041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 52210041Snilay@cs.wisc.edu # reserved for devices. 52310041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 52410041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 52510041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 52610041Snilay@cs.wisc.edu 52710041Snilay@cs.wisc.edu self.e820_table.entries = entries 52810041Snilay@cs.wisc.edu 5295330Sgblack@eecs.umich.edu # Command line 5305847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5315845Sgblack@eecs.umich.edu 'root=/dev/hda1' 53210003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 5335133Sgblack@eecs.umich.edu return self 5345133Sgblack@eecs.umich.edu 5353584Ssaidi@eecs.umich.edu 5368801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5378801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5382995Ssaidi@eecs.umich.edu self.testsys = testSystem 5392995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5404981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5414981Ssaidi@eecs.umich.edu 5428661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5438661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5448661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5458661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5468661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5478661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5488661SAli.Saidi@ARM.com else: 5498661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5508661SAli.Saidi@ARM.com 5513025Ssaidi@eecs.umich.edu if dumpfile: 5523025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5533025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5542934Sktlim@umich.edu 5552934Sktlim@umich.edu return self 556