FSConfig.py revision 10071
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 539036Sandreas.hansson@arm.comclass MemBus(CoherentBus): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 589826Sandreas.hansson@arm.comdef makeLinuxAlphaSystem(mem_mode, mdesc = None): 598713Sandreas.hansson@arm.com IO_address_space_base = 0x80000000000 604520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 614982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 624520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 634520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 642934Sktlim@umich.edu 652934Sktlim@umich.edu self = LinuxAlphaSystem() 663005Sstever@eecs.umich.edu if not mdesc: 673005Sstever@eecs.umich.edu # generic system 683304Sstever@eecs.umich.edu mdesc = SysConfig() 692995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 709036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 719036Sandreas.hansson@arm.com self.membus = MemBus() 728713Sandreas.hansson@arm.com # By default the bridge responds to all addresses above the I/O 738713Sandreas.hansson@arm.com # base address (including the PCI config space) 749164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', 758713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 769826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 778839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 788839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 792934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 802934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 812995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 822934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 832934Sktlim@umich.edu self.tsunami = BaseTsunami() 842934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 858839Sandreas.hansson@arm.com self.tsunami.ide.pio = self.iobus.master 868839Sandreas.hansson@arm.com self.tsunami.ide.config = self.iobus.master 878839Sandreas.hansson@arm.com self.tsunami.ide.dma = self.iobus.slave 888839Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.iobus.master 898839Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.iobus.master 908839Sandreas.hansson@arm.com self.tsunami.ethernet.dma = self.iobus.slave 912995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 922934Sktlim@umich.edu read_only = True)) 932934Sktlim@umich.edu self.intrctrl = IntrControl() 942953Sktlim@umich.edu self.mem_mode = mem_mode 955478Snate@binkert.org self.terminal = Terminal() 962934Sktlim@umich.edu self.kernel = binary('vmlinux') 973449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 982934Sktlim@umich.edu self.console = binary('console') 992934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1002934Sktlim@umich.edu 1018839Sandreas.hansson@arm.com self.system_port = self.membus.slave 1028706Sandreas.hansson@arm.com 1032934Sktlim@umich.edu return self 1042934Sktlim@umich.edu 1059826Sandreas.hansson@arm.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 1066765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 1076765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1086765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1096765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1109826Sandreas.hansson@arm.com self = LinuxAlphaSystem() 1119826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1126765SBrad.Beckmann@amd.com if not mdesc: 1136765SBrad.Beckmann@amd.com # generic system 1146765SBrad.Beckmann@amd.com mdesc = SysConfig() 1156765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1166765SBrad.Beckmann@amd.com 1176765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1189036Sandreas.hansson@arm.com self.piobus = NoncoherentBus() 1196893SBrad.Beckmann@amd.com 1206765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1216765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1226765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1236765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1246765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1256765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1268839Sandreas.hansson@arm.com self.tsunami.ide.pio = self.piobus.master 1278839Sandreas.hansson@arm.com self.tsunami.ide.config = self.piobus.master 1288839Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.piobus.master 1298839Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.piobus.master 1306765SBrad.Beckmann@amd.com 1316893SBrad.Beckmann@amd.com # 1327633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1337633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1346893SBrad.Beckmann@amd.com # 1358929Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1366765SBrad.Beckmann@amd.com 1376765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1386765SBrad.Beckmann@amd.com read_only = True)) 1396765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1406765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1416765SBrad.Beckmann@amd.com self.terminal = Terminal() 1426765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1436765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1446765SBrad.Beckmann@amd.com self.console = binary('console') 1456765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1466765SBrad.Beckmann@amd.com 1476765SBrad.Beckmann@amd.com return self 1486765SBrad.Beckmann@amd.com 1499826Sandreas.hansson@arm.comdef makeSparcSystem(mem_mode, mdesc = None): 1508713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1518713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1528713Sandreas.hansson@arm.com uart_pio_size = 8 1538713Sandreas.hansson@arm.com 1544486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1554486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1564486Sbinkertn@umich.edu read_only=False) 1574486Sbinkertn@umich.edu 1584486Sbinkertn@umich.edu def childImage(self, ci): 1594486Sbinkertn@umich.edu self.image.child.image_file = ci 1604486Sbinkertn@umich.edu 1613584Ssaidi@eecs.umich.edu self = SparcSystem() 1623584Ssaidi@eecs.umich.edu if not mdesc: 1633584Ssaidi@eecs.umich.edu # generic system 1643584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1653584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1669036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 1679036Sandreas.hansson@arm.com self.membus = MemBus() 1689164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1693743Sgblack@eecs.umich.edu self.t1000 = T1000() 1704104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1713743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1729826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1739826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1748839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1758839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1768839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1778839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1788839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1798839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1803584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1813898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1823898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1838839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1848713Sandreas.hansson@arm.com 1858713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1868713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1878713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1888713Sandreas.hansson@arm.com self.bridge.ranges = \ 1898713Sandreas.hansson@arm.com [ 1908713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1918713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1928713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1938713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1948713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1958713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1968713Sandreas.hansson@arm.com iob_man_addr - 1), 1978713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1988713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1998713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 2008713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 2018713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2028713Sandreas.hansson@arm.com ] 2034103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 2044103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 2054103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 2063745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 2073745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 2083745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2093584Ssaidi@eecs.umich.edu 2108839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2118706Sandreas.hansson@arm.com 2123584Ssaidi@eecs.umich.edu return self 2133584Ssaidi@eecs.umich.edu 2149826Sandreas.hansson@arm.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, 2159665Sandreas.hansson@arm.com dtb_filename = None, bare_metal=False): 2168061SAli.Saidi@ARM.com assert machine_type 2178061SAli.Saidi@ARM.com 2187586SAli.Saidi@arm.com if bare_metal: 2197586SAli.Saidi@arm.com self = ArmSystem() 2207586SAli.Saidi@arm.com else: 2217586SAli.Saidi@arm.com self = LinuxArmSystem() 2227586SAli.Saidi@arm.com 2237586SAli.Saidi@arm.com if not mdesc: 2247586SAli.Saidi@arm.com # generic system 2257586SAli.Saidi@arm.com mdesc = SysConfig() 2267586SAli.Saidi@arm.com 2277586SAli.Saidi@arm.com self.readfile = mdesc.script() 2289036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 2299036Sandreas.hansson@arm.com self.membus = MemBus() 2307586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2319164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2328839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2338839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2347586SAli.Saidi@arm.com 2357586SAli.Saidi@arm.com self.mem_mode = mem_mode 2367586SAli.Saidi@arm.com 2377586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2387586SAli.Saidi@arm.com self.realview = RealViewPBX() 2397586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2407586SAli.Saidi@arm.com self.realview = RealViewEB() 2418525SAli.Saidi@ARM.com elif machine_type == "VExpress_ELT": 2428525SAli.Saidi@ARM.com self.realview = VExpress_ELT() 2438870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2448870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 24510037SARM gem5 Developers elif machine_type == "VExpress_EMM64": 24610037SARM gem5 Developers self.realview = VExpress_EMM64() 2477586SAli.Saidi@arm.com else: 2487586SAli.Saidi@arm.com print "Unknown Machine Type" 2497586SAli.Saidi@arm.com sys.exit(1) 2507586SAli.Saidi@arm.com 2518528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2528528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 2538528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 25410071Satgutier@umich.edu # assuming we've got one; EMM64 is an exception for the moment 25510071Satgutier@umich.edu if machine_type != "VExpress_EMM64": 25610071Satgutier@umich.edu try: 25710071Satgutier@umich.edu self.realview.ide.disks = [self.cf0] 25810071Satgutier@umich.edu except: 25910071Satgutier@umich.edu self.realview.cf_ctrl.disks = [self.cf0] 26010071Satgutier@umich.edu else: 2618528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2628528SAli.Saidi@ARM.com 2638061SAli.Saidi@ARM.com if bare_metal: 2648061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2658061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2669845SAli.Saidi@ARM.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 2679845SAli.Saidi@ARM.com size = mdesc.mem())] 2688061SAli.Saidi@ARM.com else: 2698528SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2709929SAli.Saidi@ARM.com if dtb_filename: 2719929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 2727586SAli.Saidi@arm.com self.machine_type = machine_type 2738894Ssaidi@eecs.umich.edu if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2748870SAli.Saidi@ARM.com print "The currently selected ARM platforms doesn't support" 2758870SAli.Saidi@ARM.com print " the amount of DRAM you've selected. Please try" 2768870SAli.Saidi@ARM.com print " another platform" 2778894Ssaidi@eecs.umich.edu sys.exit(1) 2788528SAli.Saidi@ARM.com 27910071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 28010071Satgutier@umich.edu boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 28110071Satgutier@umich.edu 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 28210071Satgutier@umich.edu 'mem=%s root=/dev/sda1' % mdesc.mem() 28310071Satgutier@umich.edu 2849826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 2859826Sandreas.hansson@arm.com size = mdesc.mem())] 2868870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2878528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2888528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2898287SAli.Saidi@ARM.com 2908643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2918595SAli.Saidi@ARM.com boot_flags += " init=/init " 2928212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 2938713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 2947586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2957586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2967586SAli.Saidi@arm.com self.terminal = Terminal() 2977949SAli.Saidi@ARM.com self.vncserver = VncServer() 2987586SAli.Saidi@arm.com 2998839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3008706Sandreas.hansson@arm.com 3017586SAli.Saidi@arm.com return self 3027586SAli.Saidi@arm.com 3037586SAli.Saidi@arm.com 3049826Sandreas.hansson@arm.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 3055222Sksewell@umich.edu class BaseMalta(Malta): 3065222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3075222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3085222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3095222Sksewell@umich.edu 3105222Sksewell@umich.edu self = LinuxMipsSystem() 3115222Sksewell@umich.edu if not mdesc: 3125222Sksewell@umich.edu # generic system 3135222Sksewell@umich.edu mdesc = SysConfig() 3145222Sksewell@umich.edu self.readfile = mdesc.script() 3159036Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 3169036Sandreas.hansson@arm.com self.membus = MemBus() 3179164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3189826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 3198839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3208839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3215222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3225222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3235222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3245222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3255222Sksewell@umich.edu self.malta = BaseMalta() 3265222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3278839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3288839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3298839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3308839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3318839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3328839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3335222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3345222Sksewell@umich.edu read_only = True)) 3355222Sksewell@umich.edu self.intrctrl = IntrControl() 3365222Sksewell@umich.edu self.mem_mode = mem_mode 3375478Snate@binkert.org self.terminal = Terminal() 3385222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3395222Sksewell@umich.edu self.console = binary('mips/console') 3405222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3415222Sksewell@umich.edu 3428839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3438706Sandreas.hansson@arm.com 3445222Sksewell@umich.edu return self 3455222Sksewell@umich.edu 3465323Sgblack@eecs.umich.edudef x86IOAddress(port): 3475357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3488323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3495323Sgblack@eecs.umich.edu 3508858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3518713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3528713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3538713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3548713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3558713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3568713Sandreas.hansson@arm.com 3579036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 3587905SBrad.Beckmann@amd.com 3597905SBrad.Beckmann@amd.com # North Bridge 3609036Sandreas.hansson@arm.com x86_sys.iobus = NoncoherentBus() 3619164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 3628839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3638839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 3648713Sandreas.hansson@arm.com # Allow the bridge to pass through the IO APIC (two pages), 3658713Sandreas.hansson@arm.com # everything in the IO address range up to the local APIC, and 3668713Sandreas.hansson@arm.com # then the entire PCI address space and beyond 3678713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3688713Sandreas.hansson@arm.com [ 3698713Sandreas.hansson@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3708713Sandreas.hansson@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 3718713Sandreas.hansson@arm.com APIC_range_size - 1), 3728713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3738713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3748713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3758713Sandreas.hansson@arm.com Addr.max) 3768713Sandreas.hansson@arm.com ] 3778713Sandreas.hansson@arm.com 3788713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3798713Sandreas.hansson@arm.com # the local APIC (two pages) 3809164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 3818839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3828839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 3838815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3848815Sgblack@eecs.umich.edu interrupts_address_space_base + 3858858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 3868858Sgblack@eecs.umich.edu - 1)] 3877905SBrad.Beckmann@amd.com 3887905SBrad.Beckmann@amd.com # connect the io bus 3897905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3907905SBrad.Beckmann@amd.com 3918839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 3928706Sandreas.hansson@arm.com 3937905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 3947905SBrad.Beckmann@amd.com # North Bridge 3959036Sandreas.hansson@arm.com x86_sys.piobus = NoncoherentBus() 3967905SBrad.Beckmann@amd.com 3978929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 3988929Snilay@cs.wisc.edu # dma controllers 3998929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 4008929Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 4017905SBrad.Beckmann@amd.com 4027905SBrad.Beckmann@amd.com 4039826Sandreas.hansson@arm.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, 4049665Sandreas.hansson@arm.com Ruby = False): 4055613Sgblack@eecs.umich.edu if self == None: 4065613Sgblack@eecs.umich.edu self = X86System() 4075613Sgblack@eecs.umich.edu 4085133Sgblack@eecs.umich.edu if not mdesc: 4095133Sgblack@eecs.umich.edu # generic system 4105133Sgblack@eecs.umich.edu mdesc = SysConfig() 4115133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4125133Sgblack@eecs.umich.edu 4136802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4146802Sgblack@eecs.umich.edu 4155133Sgblack@eecs.umich.edu # Physical memory 41610041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 41710041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 41810041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 41910041Snilay@cs.wisc.edu excess_mem_size = \ 42010041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 42110041Snilay@cs.wisc.edu if excess_mem_size <= 0: 42210041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 42310041Snilay@cs.wisc.edu else: 42410046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 42510046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 42610046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 42710046Snilay@cs.wisc.edu 42810041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 42910041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4305613Sgblack@eecs.umich.edu 4315613Sgblack@eecs.umich.edu # Platform 4325638Sgblack@eecs.umich.edu self.pc = Pc() 4337905SBrad.Beckmann@amd.com 4347905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4357905SBrad.Beckmann@amd.com if Ruby: 4367905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4377905SBrad.Beckmann@amd.com else: 4388858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4395613Sgblack@eecs.umich.edu 4405613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4415613Sgblack@eecs.umich.edu 4425841Sgblack@eecs.umich.edu # Disks 4435841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4445841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4455841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4465841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4475841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4485841Sgblack@eecs.umich.edu 4495615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4505615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4515615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4525615Sgblack@eecs.umich.edu 4535641Sgblack@eecs.umich.edu # Set up the Intel MP table 4548323Ssteve.reinhardt@amd.com base_entries = [] 4558323Ssteve.reinhardt@amd.com ext_entries = [] 4566135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4576135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4586135Sgblack@eecs.umich.edu local_apic_id = i, 4596135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4606135Sgblack@eecs.umich.edu enable = True, 4616135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4628323Ssteve.reinhardt@amd.com base_entries.append(bp) 4635644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4646135Sgblack@eecs.umich.edu id = numCPUs, 4655644Sgblack@eecs.umich.edu version = 0x11, 4665644Sgblack@eecs.umich.edu enable = True, 4675644Sgblack@eecs.umich.edu address = 0xfec00000) 4686135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4698323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 4705644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4718323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 4725843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4738323Ssteve.reinhardt@amd.com base_entries.append(pci_bus) 4745843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4755843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4768323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4775843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4785843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4795843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4805843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4815843Sgblack@eecs.umich.edu source_bus_id = 1, 4825843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4836044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4845843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4858323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4866135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4876135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4886135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4896135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4906135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4916135Sgblack@eecs.umich.edu source_bus_id = 0, 4926135Sgblack@eecs.umich.edu source_bus_irq = irq, 4936135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4946135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4958323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4966135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4976135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4986135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4996135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 5006135Sgblack@eecs.umich.edu source_bus_id = 0, 5016135Sgblack@eecs.umich.edu source_bus_irq = irq, 5026135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5036135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5048323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5056135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5066135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5076135Sgblack@eecs.umich.edu for i in range(3, 15): 5086135Sgblack@eecs.umich.edu assignISAInt(i, i) 5098323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5108323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5115641Sgblack@eecs.umich.edu 5129826Sandreas.hansson@arm.comdef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, 5139665Sandreas.hansson@arm.com Ruby = False): 5145613Sgblack@eecs.umich.edu self = LinuxX86System() 5155613Sgblack@eecs.umich.edu 5167905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5179826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5185613Sgblack@eecs.umich.edu 5195450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5205450Sgblack@eecs.umich.edu # just to avoid corner cases. 5219826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5229232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 52310041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5245450Sgblack@eecs.umich.edu 52510041Snilay@cs.wisc.edu entries = \ 5268323Ssteve.reinhardt@amd.com [ 5278323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5289622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5299622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 53010041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 5318323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 53210041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5339898Sandreas@sandberg.pp.se range_type = 1), 5349898Sandreas@sandberg.pp.se # Reserve the last 16kB of the 32-bit address space for the 5359898Sandreas@sandberg.pp.se # m5op interface 5369898Sandreas@sandberg.pp.se X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2), 5378323Ssteve.reinhardt@amd.com ] 5385450Sgblack@eecs.umich.edu 53910041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 54010041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 54110041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 54210041Snilay@cs.wisc.edu # reserved for devices. 54310041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 54410041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 54510041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 54610041Snilay@cs.wisc.edu 54710041Snilay@cs.wisc.edu self.e820_table.entries = entries 54810041Snilay@cs.wisc.edu 5495330Sgblack@eecs.umich.edu # Command line 5505847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5515845Sgblack@eecs.umich.edu 'root=/dev/hda1' 55210003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 5535133Sgblack@eecs.umich.edu return self 5545133Sgblack@eecs.umich.edu 5553584Ssaidi@eecs.umich.edu 5568801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5578801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5582995Ssaidi@eecs.umich.edu self.testsys = testSystem 5592995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5604981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5614981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5624981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5634981Ssaidi@eecs.umich.edu 5648661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5658661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5668661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5678661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5688661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5698661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5708661SAli.Saidi@ARM.com else: 5718661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5728661SAli.Saidi@ARM.com 5733025Ssaidi@eecs.umich.edu if dumpfile: 5743025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5753025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5762934Sktlim@umich.edu 5772934Sktlim@umich.edu return self 578