/gem5/src/systemc/tests/systemc/examples/updown/ |
H A D | updown.cpp | 10 sc_in<sc_uint<1> > up; local 35 switch( (unsigned int )(up,down) ) { 52 carry_out = up&cnt_up[9]; 60 #define UP_DOWN(up, down) up, down 63 int up; member in struct:stimulus 97 sc_signal<sc_uint<1> > up; local 107 up_down_0.up(up); 110 "clock", "up", "dow [all...] |
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | breakpoint.S | 16 # Set up breakpoint to trap on M-mode fetches. 48 # Set up breakpoint to trap on M-mode reads. 68 # Set up breakpoint to trap on M-mode stores. 85 # Try to set up a second breakpoint.
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/gem5/src/cpu/pred/ |
H A D | loop_predictor.hh | 94 * Updates an unsigned counter based on up/down parameter 96 * @param up Boolean indicating if the counter is incremented/decremented 100 static inline void unsignedCtrUpdate(uint8_t &ctr, bool up, unsigned nbits) argument 103 if (up) { 111 static inline void signedCtrUpdate(int8_t &ctr, bool up, unsigned nbits) argument 113 if (up) {
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H A D | tage_base.hh | 230 * Updates an unsigned counter based on up/down parameter 232 * @param up Boolean indicating if the counter is incremented/decremented 236 static void unsignedCtrUpdate(uint8_t & ctr, bool up, unsigned nbits);
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H A D | tage_base.cc | 274 TAGEBase::unsignedCtrUpdate(uint8_t & ctr, bool up, unsigned nbits) argument 277 if (up) {
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/gem5/util/dist/test/ |
H A D | simple_bootscript.rcS | 72 /sbin/ifconfig eth0 192.168.0.${MY_ADDR} netmask 255.255.255.0 up
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/gem5/src/systemc/ext/utils/ |
H A D | endian.hh | 76 # error The file boost/detail/endian.hpp needs to be set up for your CPU type.
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/gem5/src/arch/arm/insts/ |
H A D | macromem.hh | 391 bool up; member in class:ArmISA::MicroMemOp 397 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) 409 bool up; member in class:ArmISA::MicroMemPairOp 417 dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm), 433 IntRegIndex rn, bool index, bool up, bool user, 539 IntRegIndex rn, RegIndex vd, bool single, bool up,
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H A D | macromem.cc | 58 bool index, bool up, bool user, bool writeback, 89 if (!up) 128 copy_base ? INTREG_UREG0 : rn, up, addr); 141 if (up) addr += 8; 158 copy_base ? INTREG_UREG0 : rn, up, addr); 162 copy_base ? INTREG_UREG0 : rn, up, addr); 166 copy_base ? INTREG_UREG0 : rn, up, addr); 180 *uop = new MicroStrUop(machInst, reg_idx, rn, up, addr); 183 if (up) addr += 4; 194 if (up) 56 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, bool index, bool up, bool user, bool writeback, bool load, uint32_t reglist) argument 1437 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, RegIndex vd, bool single, bool up, bool writeback, bool load, uint32_t offset) argument [all...] |
/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
H A D | cycle_model.h | 126 stack_el *up; member in struct:stack_el
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H A D | cycle_model.cpp | 74 // The simulation is then speeded up because no bus transactions occurs. 1622 new_stack_el->up = my_stack; 1633 stack_el *new_stack_el = my_stack->up; 1717 my_stack->up = NULL;
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | csr.S | 124 # catch RVTEST_PASS and kick it up to M-mode
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H A D | dirty.S | 24 # Set up MPRV with MPP=S, so loads and stores use S-mode
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/gem5/ext/systemc/src/sysc/datatypes/int/ |
H A D | sc_unsigned_subref.inc | 47 uint64 sc_unsigned_subref_r::concat_get_uint64() const // #### Speed up! 55 // #### Speed up! 62 // #### Speed up!
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H A D | sc_nbcommon.inc | 2683 // The number of bits up to and including l and r, respectively. 2831 // The number of bits up to and including l and r, respectively.
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/gem5/src/arch/arm/ |
H A D | types.hh | 93 // Made up bitfields that make life easier. 134 Bitfield<23> up; member in namespace:ArmISA
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/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | ksr1.s | 333 # A new thread is set up to "appear" as if it were executing code at
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