/gem5/src/arch/arm/ |
H A D | vtophys.cc | 76 // Check the TLBs for a translation 77 // It's possible that there is a valid translation in the tlb 99 const std::pair<bool, Addr> translation(try_translate(tc, addr)); 101 if (translation.first) 102 return translation.second; 110 const std::pair<bool, Addr> translation(try_translate(tc, vaddr)); 112 return translation.first;
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H A D | stage2_mmu.cc | 91 // while doing a translation for a stage 1 page table walk. 102 Stage2Translation *translation, int numBytes, 106 translation->setVirt( 108 translation->translateTiming(tc); 127 // while doing a translation for a stage 1 page table walk. 101 readDataTimed(ThreadContext *tc, Addr descAddr, Stage2Translation *translation, int numBytes, Request::Flags flags) argument
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H A D | tlb.hh | 73 * Check if a TLB translation should be forced to fail. 75 * @param req Request requiring a translation. 131 // Address translation instructions (eg AT S1E0R_Xt) need to be handled 132 // in special ways during translation because they could need to act 144 * Determine the EL to use for the purpose of a translation given 145 * a specific translation type. If the translation type doesn't 156 // Certain address translation instructions will intercept the IPA but the 160 bool directToStage2; // Indicates whether all translation requests should 206 * @param vmid The virtual machine ID used for stage 2 translation [all...] |
H A D | stage2_mmu.hh | 61 /** Port to issue translation requests from */ 68 /** This translation class is used to trigger the data fetch once a timing 69 translation returns the translated physical address */ 118 Stage2Translation *translation, int numBytes,
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H A D | tlb.cc | 566 Translation *translation, bool &delay, bool timing) 619 // Get the translation type from the actuall table entry 623 // If this is the second stage of translation and the request is for a 809 // If this is the second stage of translation and the request is for a 1021 // 3) Address translation instructions, other than ATS1E1RP and 1037 Translation *translation, bool &delay, bool timing, 1142 Fault fault = getResultTe(&te, req, tc, mode, translation, timing, 1148 // request that triggered the translation 1192 // translation has completed (i.e., there is a table entry). 1243 Translation *translation, Mod 565 translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) argument 1036 translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) argument 1242 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType) argument 1259 translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType, bool callFromS2) argument 1452 getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, TLB::ArmTranslationType tranType) argument 1519 getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) argument [all...] |
/gem5/src/arch/generic/ |
H A D | tlb.cc | 43 panic("Generic translation shouldn't be used in full system mode.\n"); 56 Translation *translation, Mode mode) 58 assert(translation); 59 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 55 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument
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H A D | tlb.hh | 68 * Signal that the translation has been delayed due to a hw page table 84 * @ return Is the instruction that requested this translation squashed? 96 Translation *translation, Mode mode) = 0; 104 * Do post-translation physical address finalization. 107 * post-translation massaging of physical addresses. For example, 158 Translation *translation, Mode mode) override;
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/gem5/src/arch/x86/ |
H A D | tlb.hh | 112 Translation *translation, Mode mode, 129 Translation *translation, Mode mode) override; 132 * Do post-translation physical address finalization. 135 * need post-translation updates. Such physical addresses are
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H A D | pagetable_walker.hh | 108 TLB::Translation * translation; member in class:X86ISA::Walker::WalkerState 120 translation(_translation), 162 Fault start(ThreadContext * _tc, BaseTLB::Translation *translation, 178 // Wrapper for checking for squashes before starting a translation.
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H A D | tlb.cc | 270 ThreadContext *tc, Translation *translation, 332 // If paging is enabled, do the translation. 352 Fault fault = walker->start(tc, translation, req, mode); 438 Translation *translation, Mode mode) 441 assert(translation); 443 TLB::translate(req, tc, translation, mode, delayedResponse, true); 445 translation->finish(fault, req, tc, mode); 447 translation->markDelayed(); 269 translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing) argument 437 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument
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H A D | pagetable_walker.cc | 196 currState->translation->squashed()) { 203 // finish the translation which will delete the translation object 204 currState->translation->finish( 217 // check the next translation request, if it exists 637 * Finish the translation. Now that we know the right entry is 648 translation->finish(fault, req, tc, mode); 651 translation->finish(timingFault, req, tc, mode);
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/gem5/src/arch/mips/ |
H A D | tlb.hh | 119 Translation *translation, Mode mode) override;
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H A D | tlb.cc | 325 Translation *translation, Mode mode) 327 assert(translation); 328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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/gem5/src/arch/riscv/ |
H A D | tlb.hh | 118 Translation *translation, Mode mode) override;
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H A D | tlb.cc | 378 Translation *translation, Mode mode) 380 assert(translation); 381 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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/gem5/src/arch/power/ |
H A D | tlb.cc | 326 Translation *translation, Mode mode) 328 assert(translation); 329 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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H A D | tlb.hh | 169 Translation *translation, Mode mode) override;
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/gem5/src/arch/alpha/ |
H A D | tlb.hh | 148 Translation *translation, Mode mode) override;
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H A D | tlb.cc | 612 Translation *translation, Mode mode) 614 assert(translation); 615 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 611 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument
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/gem5/src/gpu-compute/ |
H A D | gpu_tlb.hh | 106 * Signal that the translation has been delayed due to a hw page 183 Translation *translation, Mode mode, bool &delayedResponse, 229 Translation *translation, Mode mode, 345 // When was the req for this translation issued
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H A D | GPU.py | 157 translation = Param.Bool(False, "address translation"); variable in class:Shader
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H A D | gpu_tlb.cc | 671 // If paging is enabled, do the translation. 702 Translation *translation, Mode mode, 779 // If paging is enabled, do the translation. 915 Translation *translation, Mode mode, int &latency) 918 assert(translation); 920 Fault fault = GpuTLB::translate(req, tc, translation, mode, 924 translation->finish(fault, req, tc, mode); 1290 DPRINTF(GPUTLB, "Failed sending translation request to " 1295 DPRINTF(GPUTLB, "Sent translation request to lower level " 1347 /** we add an extra cycle in the return path of the translation 701 translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing, int &latency) argument 914 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, int &latency) argument [all...] |
/gem5/src/arch/sparc/ |
H A D | tlb.hh | 112 * @param real is this a real->phys or virt->phys translation 175 Translation *translation, Mode mode) override;
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H A D | tlb.cc | 522 // cache translation date for next translation 760 // cache translation date for next translation 847 Translation *translation, Mode mode) 849 assert(translation); 850 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 846 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument
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/gem5/src/cpu/simple/ |
H A D | timing.cc | 466 DataTranslation<TimingSimpleCPU *> *translation 468 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 555 DataTranslation<TimingSimpleCPU *> *translation = 557 thread->dtb->translateTiming(req, thread->getTC(), translation, mode); 606 DataTranslation<TimingSimpleCPU *> *translation 608 thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
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