/gem5/src/arch/arm/kvm/ |
H A D | gic.cc | 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 22 * contributors may be used to endorse or promote products derived from 209 // Should only occur due to CPU switches 210 if (use_kvm) // from simulation to KVM emulation 212 // otherwise, drain() already sync'd the state back to the GicV2 278 // During Kvm->GicV2 state transfer, writes to th 287 copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to, ContextID ctx, Addr daddr) argument 296 copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to, ContextID ctx, Addr daddr) argument 305 copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to, Addr daddr, size_t size) argument 314 clearBankedDistRange(BaseGicRegisters* to, Addr daddr, size_t size) argument 323 copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to, Addr daddr, size_t size) argument 331 clearDistRange(BaseGicRegisters* to, Addr daddr, size_t size) argument 339 copyGicState(BaseGicRegisters* from, BaseGicRegisters* to) argument [all...] |
H A D | gic.hh | 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 22 * contributors may be used to endorse or promote products derived from 53 * This class defines a high-level interface to the KVM in-kernel GIC 54 * model. It exposes an API that is similar to that of 64 * it up to the virtual memory system. 69 * @param it_lines Number of interrupt lines to suppor [all...] |
/gem5/configs/example/ |
H A D | garnet_synth_traffic.py | 12 # contributors may be used to endorse or promote products derived from 59 Takes decimal value between 0 to 1 (eg. 0.225). \ 71 Set to -1 to disable.") 75 Set to -1 to disable.") 78 help="Only send to this destination.\ 79 Set to -1 to disable.") 84 Set to [all...] |
/gem5/src/mem/ruby/system/ |
H A D | RubySystem.py | 12 # contributors may be used to endorse or promote products derived from 39 buffers are enforced to have randomization; otherwise, a message \ 40 buffer set its own flag to enable/disable randomization)");
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.py | 12 # contributors may be used to endorse or promote products derived from 38 buffer_size = Param.Unsigned(0, "Maximum number of entries to buffer \ 41 enqueue times (enforced to have \ 45 master = MasterPort("Master port to MessageBuffer receiver")
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/gem5/src/cpu/testers/garnet_synthetic_traffic/ |
H A D | GarnetSyntheticTraffic.py | 12 # contributors may be used to endorse or promote products derived from 41 num_packets_max = Param.Int(-1, "Max number of packets to send. \ 42 Default is to keep sending till simulation ends") 45 single_dest = Param.Int(-1, "Send only to this dest. \ 49 inj_vnet = Param.Int(-1, "Vnet to inject in. \ 51 Default is to inject in all three vnets") 55 due to lack of progress") 56 test = MasterPort("Port to the memory system to test") 57 system = Param.System(Parent.any, "System we belong to") [all...] |
/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | hppa.s | 6 ; Permission to use, copy, modify and distribute this software and 37 ; arg0: ptr to function (helper) to call once curr is suspended 39 ; arg1: 1'th arg to *arg0. 40 ; arg2: 2'th arg to *arg0. 48 stw %rp,-20(%sp) ; save rp to old frame-marker 68 copy %arg0,%r22 ; helper to be called by $$dyncall 69 copy %sp,%arg0 ; pass current sp as arg0 to helper 94 bv %r0(%rp) ; return to caller 106 stw %rp,-20(%sp) ; save rp to ol [all...] |
H A D | ksr1.s | 5 * Permission to use, copy, modify and distribute this software and 31 # and a pointer to a constant block. The address of function `f' is 41 # Note, by the way, that a pointer to a function is passed as a 42 # pointer to the constant area, and the constant area has the text 54 # Calls to those procedures branch to a 16 byte offset (4 instrs) in 55 # to the procedure to skip those instructions. 65 # Calls that want the returned structure branch directly to the 67 # return value branche 16 bytes in to th [all...] |
H A D | hppa_b.s | 4 ; Permission to use, copy, modify and distribute this software and 21 ; from implementation to implementation. I took eight instructions in a loop 22 ; for every test (execute eight instructions and loop to the start). 33 ; Just do nothing, only return to caller. This procedure is called by 54 stw %rp,-20(%sp) ; save return-pointer to frame-marker 60 copy %r3,%r22 ; copy the procedure label to r22, ... 61 .CALL ; ...this is the input to $$dyncall 104 bv %r0(%rp) ; return to caller 118 stw %rp,-20(%sp) ; save return-pointer to frame-marker 142 bv %r0(%rp) ; return to calle [all...] |
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | access.S | 23 # jalr to an illegal address should commit (hence should write rd). 24 # after the pc is set to rs1, an access exception should be raised. 32 # A load to an illegal address should not commit.
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H A D | breakpoint.S | 16 # Set up breakpoint to trap on M-mode fetches. 48 # Set up breakpoint to trap on M-mode reads. 68 # Set up breakpoint to trap on M-mode stores. 85 # Try to set up a second breakpoint.
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/gem5/ext/systemc/src/sysc/datatypes/int/ |
H A D | sc_nbfriends.inc | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 30 The functions here try to use faster algorithms in case 223 // One extra digit for d is allocated to simplify vec_div_*(). 286 // One extra digit for d is allocated to simplify vec_div_*().
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H A D | sc_signed_bitref.inc | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 45 // implicit conversion to uint64
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H A D | sc_unsigned_bitref.inc | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 45 // implicit conversion to uint64
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/gem5/src/systemc/dt/int/ |
H A D | sc_nbfriends.inc | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 30 The functions here try to use faster algorithms in case 191 // One extra digit for d is allocated to simplify vec_div_*(). 242 // One extra digit for d is allocated to simplify vec_div_*().
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H A D | sc_nbcommon.inc | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 22 sc_nbcommon.cpp -- Functions common to both sc_signed and sc_unsigned. 28 to ensure only one version of each function, regardless 29 of the class that they interface to. 300 // Cases to consider when computing u + v: 482 // Cases to consider when computing u + v: 656 // Cases to consider when computing u * v: 778 // Cases to conside [all...] |
H A D | sc_signed_bitref.inc | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 45 // implicit conversion to uint64
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H A D | sc_unsigned_bitref.inc | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 45 // implicit conversion to uint64
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | csr.S | 29 # If running in M mode, use mstatus.MPP to check existence of U mode. 30 # Otherwise, if in S mode, then U mode must exist and we don't need to check. 85 # jump to user land 110 # We should only fall through to this if scall failed. 124 # catch RVTEST_PASS and kick it up to M-mode 135 # Return to user mode, but skip the trapping instruction.
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H A D | scall.S | 33 # If running in M mode, use mstatus.MPP to check existence of U mode. 34 # Otherwise, if in S mode, then U mode must exist and we don't need to check.
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | traffic_gen.hh | 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 22 * contributors may be used to endorse or promote products derived from 60 * The traffic generator has a single master port that is used to send 67 * forward to create very complex behaviours, simply by arranging them 75 * The config file to parse. 83 * This method resolves a relative path to 109 uint32_t to; member in struct:TrafficGen::Transition [all...] |
/gem5/src/systemc/tests/include/ |
H A D | SimpleBusAT.h | 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 6 Accellera licenses this file to you under the Apache License, Version 2.0 12 Unless required by applicable law or agreed to in writing, software 114 it->second.to = decodeSocket; 135 // Not needed to send END_REQ to initiator 142 // only send END_REQ to initiator if BEGIN_RESP was not already send 155 // reset to destination port (we must not send END_RESP to target) 156 it->second.to 348 addPendingTransaction(transaction_type& trans, initiator_socket_type* to, int initiatorId) argument 360 initiator_socket_type* to; member in struct:SimpleBusAT::ConnectionInfo [all...] |
/gem5/src/systemc/channel/ |
H A D | sc_clock.cc | 12 * contributors may be used to endorse or promote products derived from 56 ClockTick(::sc_core::sc_clock *clock, bool to, argument 60 funcWrapper(clock, to ? &::sc_core::sc_clock::tickUp : 63 name += std::string(to ? "_posedge_action" : "_negedge_action");
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ua/ |
H A D | lrsc.S | 45 # have each core add its coreid+1 to foo 1024 times 56 # wait for all cores to finish
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/gem5/system/alpha/console/ |
H A D | dbmentry.S | 14 * contributors may be used to endorse or promote products derived from 38 /* return address and padding to octaword align */ 49 Other processors spin here waiting to get their stacks from 175 stq_c v0,0(a0) # attempt to acquire lock 178 ret zero,(ra) # return to caller (v0 is 1) 200 mov a2, t2 # what to spin on 206 call_pal PAL_SWPCTX_ENTRY # switch to pcb
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