Searched refs:tRAS (Results 1 - 5 of 5) sorted by relevance

/gem5/src/mem/
H A DDRAMCtrl.py167 tRAS = Param.Latency("ACT to PRE delay") variable in class:DRAMCtrl
245 # tRC - assumed to be tRAS + tRP
363 tRAS = '35ns' variable in class:DDR3_1600_8x8
461 tRAS = '21.6ns' variable in class:HMC_2500_1x32
519 tRAS = '33ns' variable in class:DDR3_2133_8x8
592 tRAS = '32ns' variable in class:DDR4_2400_16x4
759 tRAS = '42ns' variable in class:LPDDR2_S4_1066_1x32
853 tRAS = '42ns' variable in class:WideIO_200_1x128
923 tRAS = '42ns' variable in class:LPDDR3_1600_1x32
1037 tRAS variable in class:GDDR5_4000_2x32
1117 tRAS = '33ns' variable in class:HBM_1000_4H_1x128
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H A Ddrampower.cc80 timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK);
85 timingSpec.RAS = divCeil(p->tRAS, p->tCK);
H A Ddram_ctrl.hh996 const Tick tRAS; member in class:DRAMCtrl
H A Ddram_ctrl.cc88 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
984 // The next access has to respect tRAS for this bank
985 bank_ref.preAllowedAt = act_tick + tRAS;
/gem5/configs/dram/
H A Dlow_power_sweep.py159 #The itt value when set to (tRAS + tRP + tCK) covers the case where
165 pd_entry_time = (system.mem_ctrls[0].tRAS.value +

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