Searched refs:nsacr (Results 1 - 5 of 5) sorted by relevance
/gem5/src/arch/arm/insts/ |
H A D | static_inst.hh | 203 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, argument 244 if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1') 422 NSACR nsacr, FPEXC fpexc,
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H A D | static_inst.cc | 700 NSACR nsacr, FPEXC fpexc, 715 if (nsacr.nsasedis) 717 if (nsacr.cp10 == 0) 744 if (nsacr.nsasedis) 746 if (nsacr.cp10)
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/gem5/src/arch/arm/ |
H A D | utility.cc | 701 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) 796 ok &= (mode != MODE_FIQ) || !nsacr.rfr; 805 ok &= (mode != MODE_FIQ) || !nsacr.rfr; 700 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) argument
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H A D | utility.hh | 355 CPSR cpsr, SCR scr, NSACR nsacr,
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H A D | isa.cc | 500 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 502 if (!nsacr.cp10) cpacrMask.cp10 = 0; 503 if (!nsacr.cp11) cpacrMask.cp11 = 0; 843 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 845 if (!nsacr.cp10) cpacrMask.cp10 = 0; 846 if (!nsacr.cp11) cpacrMask.cp11 = 0;
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