/gem5/src/dev/ |
H A D | isa_fake.cc | 101 data = pkt->getLE<uint64_t>(); 104 data = pkt->getLE<uint32_t>(); 107 data = pkt->getLE<uint16_t>(); 110 data = pkt->getLE<uint8_t>(); 129 retData64 = pkt->getLE<uint64_t>(); 132 retData32 = pkt->getLE<uint32_t>(); 135 retData16 = pkt->getLE<uint16_t>(); 138 retData8 = pkt->getLE<uint8_t>();
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/gem5/src/dev/alpha/ |
H A D | tsunami_io.cc | 161 (uint32_t)pkt->getLE<uint8_t>()); 167 mask1 = ~(pkt->getLE<uint8_t>()); 180 mask2 = pkt->getLE<uint8_t>(); 185 picr &= ~(1 << (pkt->getLE<uint8_t>() & 0xF)); 190 mode1 = pkt->getLE<uint8_t>(); 193 mode2 = pkt->getLE<uint8_t>(); 196 pitimer.writeCounter(0, pkt->getLE<uint8_t>()); 199 pitimer.writeCounter(1, pkt->getLE<uint8_t>()); 202 pitimer.writeCounter(2, pkt->getLE<uint8_t>()); 205 pitimer.writeControl(pkt->getLE<uint8_ [all...] |
H A D | tsunami_pchip.cc | 174 wsba[0] = pkt->getLE<uint64_t>(); 177 wsba[1] = pkt->getLE<uint64_t>(); 180 wsba[2] = pkt->getLE<uint64_t>(); 183 wsba[3] = pkt->getLE<uint64_t>(); 186 wsm[0] = pkt->getLE<uint64_t>(); 189 wsm[1] = pkt->getLE<uint64_t>(); 192 wsm[2] = pkt->getLE<uint64_t>(); 195 wsm[3] = pkt->getLE<uint64_t>(); 198 tba[0] = pkt->getLE<uint64_t>(); 201 tba[1] = pkt->getLE<uint64_ [all...] |
H A D | tsunami_cchip.cc | 187 regnum, pkt->getSize(), pkt->getLE<uint64_t>()); 204 pkt->getAddr(), pkt->getLE<uint64_t>()); 219 dim[number] = pkt->getLE<uint64_t>(); 256 ipreq = (pkt->getLE<uint64_t>() >> 12) & 0xF; 265 ipintr = (pkt->getLE<uint64_t>() >> 8) & 0xF; 273 itintr = (pkt->getLE<uint64_t>() >> 4) & 0xF; 280 if (pkt->getLE<uint64_t>() & 0x10000000) 312 dim[number] = pkt->getLE<uint64_t>(); 362 clearIPI(pkt->getLE<uint64_t>()); 365 clearITI(pkt->getLE<uint64_ [all...] |
H A D | backdoor.cc | 141 pkt->getLE<uint32_t>()); 192 pkt->getLE<uint64_t>()); 206 uint64_t val = pkt->getLE<uint64_t>();
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/gem5/src/mem/ |
H A D | packet_access.hh | 80 Packet::getLE() const function in class:Packet 94 return getLE<T>();
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/gem5/src/dev/x86/ |
H A D | i8254.cc | 73 pit.writeCounter(offset, pkt->getLE<uint8_t>()); 75 pit.writeControl(pkt->getLE<uint8_t>());
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H A D | cmos.cc | 73 address = pkt->getLE<uint8_t>(); 76 writeRegister(address, pkt->getLE<uint8_t>());
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H A D | speaker.cc | 61 SpeakerControl val = pkt->getLE<uint8_t>();
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H A D | i8237.cc | 103 uint8_t command = pkt->getLE<uint8_t>();
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/gem5/src/dev/arm/ |
H A D | rtc_pl031.cc | 95 data = pkt->getLE<uint32_t>(); 134 matchVal = pkt->getLE<uint32_t>(); 139 timeVal = pkt->getLE<uint32_t>(); 146 maskInt = pkt->getLE<uint32_t>(); 149 if (pkt->getLE<uint32_t>()) {
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H A D | timer_a9global.cc | 142 pkt->getLE<uint32_t>(), daddr); 168 pkt->getLE<uint32_t>(), daddr); 179 control = pkt->getLE<uint32_t>(); 196 cmpVal |= (uint64_t)pkt->getLE<uint32_t>(); 200 cmpVal |= ((uint64_t)pkt->getLE<uint32_t>() << 32); 203 autoIncValue = pkt->getLE<uint32_t>();
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H A D | timer_cpulocal.cc | 200 timerLoadValue = pkt->getLE<uint32_t>(); 205 restartTimerCounter(pkt->getLE<uint32_t>()); 209 timerControl = pkt->getLE<uint32_t>(); 221 watchdogLoadValue = pkt->getLE<uint32_t>(); 227 restartWatchdogCounter(pkt->getLE<uint32_t>()); 233 watchdogControl = pkt->getLE<uint32_t>(); 253 watchdogDisableReg = pkt->getLE<uint32_t>();
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H A D | rv_ctrl.cc | 147 sysLock.lockVal = pkt->getLE<uint16_t>(); 154 flags = pkt->getLE<uint32_t>(); 160 scData = pkt->getLE<uint32_t>(); 166 CfgCtrlReg req = pkt->getLE<uint32_t>(); 198 daddr, pkt->getLE<uint32_t>());
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H A D | timer_sp804.cc | 117 pkt->getLE<uint32_t>(), daddr); 142 pkt->getLE<uint32_t>(), daddr); 145 loadValue = pkt->getLE<uint32_t>(); 154 control = pkt->getLE<uint32_t>(); 167 loadValue = pkt->getLE<uint32_t>();
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H A D | pl011.cc | 143 data = pkt->getLE<uint32_t>(); 180 pkt->getLE<uint8_t>(), pkt->getSize()); 189 data = pkt->getLE<uint8_t>(); 192 data = pkt->getLE<uint16_t>(); 195 data = pkt->getLE<uint32_t>();
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H A D | vgic.cc | 247 daddr, pkt->getLE<uint32_t>()); 251 vid->vctrl = pkt->getLE<uint32_t>(); 254 vid->VMPriMask = pkt->getLE<uint32_t>(); 260 uint32_t w = pkt->getLE<uint32_t>(); 276 pkt->getLE<uint32_t>(), daddr); 294 daddr, pkt->getLE<uint32_t>()); 310 vid->hcr = pkt->getLE<uint32_t>(); 315 uint32_t d = pkt->getLE<uint32_t>(); 335 vid->LR[(daddr - GICH_LR0) >> 2] = pkt->getLE<uint32_t>();
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H A D | vio_mmio.cc | 176 DPRINTF(VIOIface, " value: 0x%x\n", pkt->getLE<uint32_t>()); 178 write(offset, pkt->getLE<uint32_t>());
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H A D | smmu_v3.cc | 623 pkt->getLE<uint64_t>() : pkt->getLE<uint32_t>()); 628 regs.cr0 = regs.cr0ack = pkt->getLE<uint32_t>(); 639 pkt->getLE<uint32_t>(); 648 pkt->getLE<uint32_t>(); 655 pkt->getLE<uint32_t>(); 663 pkt->getLE<uint64_t>(); 672 pkt->getLE<uint64_t>(); 681 pkt->getLE<uint64_t>(); 689 pkt->getLE<uint64_ [all...] |
/gem5/src/dev/virtio/ |
H A D | pci.cc | 176 vio.setGuestFeatures(pkt->getLE<uint32_t>()); 182 vio.setQueueAddress(pkt->getLE<uint32_t>()); 192 vio.setQueueSelect(pkt->getLE<uint16_t>()); 198 queueNotify = pkt->getLE<uint16_t>(); 204 uint8_t status(pkt->getLE<uint8_t>());
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/gem5/src/dev/storage/ |
H A D | ide_ctrl.cc | 210 (uint32_t)pkt->getLE<uint8_t>()); 234 (uint32_t)pkt->getLE<uint16_t>()); 248 (uint32_t)pkt->getLE<uint32_t>()); 269 deviceTiming = pkt->getLE<uint8_t>(); 272 udmaControl = pkt->getLE<uint8_t>(); 275 replaceBits(ideConfig, 7, 0, pkt->getLE<uint8_t>()); 278 replaceBits(ideConfig, 15, 8, pkt->getLE<uint8_t>()); 285 offset, (uint32_t)pkt->getLE<uint8_t>()); 290 udmaControl = pkt->getLE<uint16_t>(); 293 primaryTiming = pkt->getLE<uint16_ [all...] |
/gem5/src/dev/pci/ |
H A D | device.cc | 252 (uint32_t)pkt->getLE<uint8_t>()); 259 (uint32_t)pkt->getLE<uint16_t>()); 266 (uint32_t)pkt->getLE<uint32_t>()); 313 config.interruptLine = pkt->getLE<uint8_t>(); 316 config.cacheLineSize = pkt->getLE<uint8_t>(); 319 config.latencyTimer = pkt->getLE<uint8_t>(); 334 (uint32_t)pkt->getLE<uint8_t>()); 339 config.command = pkt->getLE<uint8_t>(); 342 config.status = pkt->getLE<uint8_t>(); 345 config.cacheLineSize = pkt->getLE<uint8_ [all...] |
H A D | copy_engine.cc | 311 uint64_t val M5_VAR_USED = pkt->getLE<uint64_t>(); 315 uint32_t val M5_VAR_USED = pkt->getLE<uint32_t>(); 319 uint16_t val M5_VAR_USED = pkt->getLE<uint16_t>(); 323 uint8_t val M5_VAR_USED = pkt->getLE<uint8_t>(); 339 regs.intrctrl.master_int_enable(bits(pkt->getLE<uint8_t>(), 0, 1)); 377 cr.ctrl(pkt->getLE<uint16_t>()); 391 cr.descChainAddr = pkt->getLE<uint64_t>(); 393 cr.descChainAddr = (uint64_t)pkt->getLE<uint32_t>() | 399 cr.descChainAddr = ((uint64_t)pkt->getLE<uint32_t>() << 32) | 405 cr.command(pkt->getLE<uint8_ [all...] |
/gem5/src/arch/x86/ |
H A D | memhelpers.hh | 59 mem = pkt->getLE<uint8_t>(); 62 mem = pkt->getLE<uint16_t>(); 65 mem = pkt->getLE<uint32_t>(); 68 mem = pkt->getLE<uint64_t>(); 81 std::array<T, N> real_mem = pkt->getLE<std::array<T, N> >();
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/gem5/src/gpu-compute/ |
H A D | dispatcher.cc | 169 data_val = pkt->getLE<uint8_t>(); 172 data_val = pkt->getLE<uint16_t>(); 175 data_val = pkt->getLE<uint32_t>(); 178 data_val = pkt->getLE<uint64_t>();
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