Searched refs:descAddr (Results 1 - 4 of 4) sorted by relevance
/gem5/src/arch/arm/ |
H A D | stage2_mmu.cc | 64 Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, argument 71 req->setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0); 101 Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr, argument 107 descAddr, numBytes, flags | Request::PT_WALK, masterId);
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H A D | stage2_mmu.hh | 115 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, 117 void readDataTimed(ThreadContext *tc, Addr descAddr,
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H A D | table_walker.cc | 1976 TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes, argument 1983 descAddr, currState->stage2Req); 1985 // If this translation has a stage 2 then we know descAddr is an IPA and 1997 stage2Mmu->readDataTimed(currState->tc, descAddr, tran, numBytes, 2002 currState->vaddr, descAddr, data, numBytes, flags, 2021 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, event, data, 2030 port->dmaAction(MemCmd::ReadReq, descAddr, numBytes, NULL, data, 2035 descAddr, numBytes, flags, masterId);
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H A D | table_walker.hh | 948 bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
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