/gem5/src/sim/ |
H A D | DVFSHandler.py | 44 # and manages all the source clock domains (SrcClockDomain) it is configured to 53 domains = VectorParam.SrcClockDomain([], "list of domains") 56 sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain,
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H A D | clock_domain.cc | 54 #include "params/SrcClockDomain.hh" 80 SrcClockDomain::SrcClockDomain(const Params *p) : function in class:SrcClockDomain 115 SrcClockDomain::clockPeriod(Tick clock_period) 139 SrcClockDomain::perfLevel(PerfLevel perf_level) 157 void SrcClockDomain::signalPerfLevelUpdate() 168 SrcClockDomain::serialize(CheckpointOut &cp) const 175 SrcClockDomain::unserialize(CheckpointIn &cp) 182 SrcClockDomain::startup() 189 SrcClockDomain * [all...] |
H A D | voltage_domain.hh | 63 typedef SrcClockDomain::PerfLevel PerfLevel; 102 * Register a SrcClockDomain with this voltage domain. 103 * @param src_clock_domain The SrcClockDomain to register. 105 void registerSrcClockDom(SrcClockDomain *src_clock_dom) { 155 typedef std::vector<SrcClockDomain *> SrcClockChildren;
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H A D | dvfs_handler.hh | 77 typedef SrcClockDomain::DomainID DomainID; 78 typedef SrcClockDomain::PerfLevel PerfLevel; 137 SrcClockDomain *d = findDomain(domain_id); 144 "SrcClockDomain %s. Returning 0\n", name(), perf_level, d->name()); 181 typedef std::map<DomainID, SrcClockDomain*> Domains; 192 SrcClockDomain* sysClkDomain; 200 SrcClockDomain *findDomain(DomainID domain_id) const {
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H A D | ClockDomain.py | 52 class SrcClockDomain(ClockDomain): class in inherits:ClockDomain 53 type = 'SrcClockDomain'
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H A D | clock_domain.hh | 57 #include "params/SrcClockDomain.hh" 171 class SrcClockDomain : public ClockDomain class in inherits:ClockDomain 177 SrcClockDomain(const Params *p);
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/gem5/tests/configs/ |
H A D | o3-timing-ruby.py | 41 clk_domain = SrcClockDomain(clock = '1GHz')) 45 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
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H A D | twosys-tsunami-simple-atomic.py | 42 test_sys.clk_domain = SrcClockDomain(clock = '1GHz', 52 test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 57 test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', 77 drive_sys.clk_domain = SrcClockDomain(clock = '1GHz', 87 drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz', 92 drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
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H A D | o3-timing-mp-ruby.py | 41 clk_domain = SrcClockDomain(clock = '1GHz')) 45 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
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H A D | simple-atomic-mp-ruby.py | 40 clk_domain = SrcClockDomain(clock = '1GHz')) 44 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
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H A D | t1000-simple-atomic.py | 40 system.clk_domain = SrcClockDomain(clock = '1GHz', 42 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
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H A D | simple-timing-ruby.py | 68 system.clk_domain = SrcClockDomain(clock = '1GHz', 73 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 80 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | simple-timing-mp-ruby.py | 68 system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz')) 72 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 77 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
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H A D | memtest-ruby.py | 78 system.clk_domain = SrcClockDomain(clock = '1GHz', 83 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 95 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | memtest.py | 44 system.clk_domain = SrcClockDomain(clock = '1GHz', 49 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
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H A D | memtest-filter.py | 44 system.clk_domain = SrcClockDomain(clock = '1GHz', 49 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
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H A D | pc-simple-timing-ruby.py | 62 system.clk_domain = SrcClockDomain(clock = '1GHz', 64 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 72 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | tgen-simple-mem.py | 54 clk_domain = SrcClockDomain(clock = '1GHz',
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H A D | tgen-dram-ctrl.py | 54 clk_domain = SrcClockDomain(clock = '1GHz',
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/gem5/tests/gem5/memory/ |
H A D | memtest-run.py | 45 system.clk_domain = SrcClockDomain(clock = '1GHz', 50 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
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/gem5/util/tlm/conf/ |
H A D | tlm_master.py | 58 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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H A D | tlm_slave.py | 60 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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H A D | tlm_elastic_slave.py | 80 system.clk_domain = SrcClockDomain(clock = '1GHz', 88 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
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/gem5/configs/learning_gem5/part3/ |
H A D | ruby_test.py | 51 system.clk_domain = SrcClockDomain()
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/gem5/util/tlm/examples/ |
H A D | tlm_elastic_slave_with_l2.py | 87 system.clk_domain = SrcClockDomain(clock = '1GHz', 95 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
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