Searched refs:READ (Results 1 - 14 of 14) sorted by relevance
/gem5/src/mem/qos/ |
H A D | turnaround_policy_ideal.cc | 79 bus_state = MemCtrl::READ; 82 bus_state = ((memCtrl->getBusState() == MemCtrl::READ) ? 83 MemCtrl::WRITE : MemCtrl::READ); 92 (bus_state == MemCtrl::READ)? "READ" : "WRITE");
|
H A D | mem_ctrl.cc | 55 busState(READ), busStateNext(READ) 99 (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos], 102 if (dir == READ) { 139 (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos]); 155 (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos], 158 if (dir == READ) { 209 (dir == READ) ? readQueueSizes[qos]: writeQueueSizes[qos]); 257 if ((!getTotalReadQueueSize() && bus_state == MemCtrl::READ) || 259 // READ/WRIT [all...] |
H A D | mem_sink.cc | 180 logRequest(pkt->isRead()? READ : WRITE, 213 std::vector<PacketQueue>* queue_ptr = (busState == READ ? &readQueue : 218 (busState == WRITE ? "WRITE" : "READ")); 244 __func__, (busState == READ? "READ" : "WRITE"), 285 logResponse(pkt->isRead()? READ : WRITE, 299 if (busState == READ && retryRdReq) {
|
H A D | mem_ctrl.hh | 65 enum BusState { READ, WRITE }; enumerator in enum:QoS::MemCtrl::BusState 71 /** QoS Bus Turnaround Policy: selects the bus direction (READ/WRITE) */ 135 /** Count the number of turnarounds READ to WRITE */ 137 /** Count the number of turnarounds WRITE to READ */ 139 /** Count the number of times bus staying in READ state */ 200 * Returns next bus direction (READ or WRITE) 206 * Set current bus direction (READ or WRITE) 296 * Gets a READ queue size 314 * Gets the total combined READ queues size 381 "QoSMemCtrl::escalate master %s negative READ " [all...] |
/gem5/ext/ply/example/BASIC/ |
H A D | linear.bas | 5 10 READ A1, A2, A3, A4 8 30 READ B1, B2
|
H A D | sales.bas | 2 20 READ P(I) 6 60 READ S(I,J)
|
H A D | maxsin.bas | 2 10 READ D
|
H A D | gcd.bas | 2 20 READ A,B,C
|
/gem5/src/gpu-compute/ |
H A D | vector_register_file.hh | 58 READ = 0x01, member in class:VrfAccessType 60 RD_WR = READ | WRITE
|
/gem5/ext/drampower/src/ |
H A D | CmdScheduler.h | 52 #define READ 0 macro 99 commandItem PreRDWR; // the latest scheduled READ or WRITE command. 104 // the scheduled READ or WRITE commands are stored in RDWR.
|
H A D | CmdScheduler.cc | 129 PreRDWR.Type = READ; 165 transType = READ; 355 case READ: 378 case READ: 503 if (transType == READ) { 563 if ((PreType == WRITE) && (CurrentType == READ)) { 593 } else if (PreType == WRITE && CurrentType == READ) { 599 if ((PreType == READ) && (CurrentType == WRITE)) {
|
/gem5/src/systemc/tests/systemc/misc/sim_tests/simple_cpu/ |
H A D | simple_cpu.cpp | 40 #define READ 0 macro
|
/gem5/src/mem/ |
H A D | dram_ctrl.cc | 488 logRequest(MemCtrl::READ, pkt->masterId(), pkt->qosValue(), 594 DPRINTF(DRAM, "===READ QUEUE===\n\n"); 1346 (busState==MemCtrl::READ)?"READ":"WRITE", 1350 if (busState == READ) { 1411 if (busState == READ) { 1454 "DRAM controller checking READ queue [%d] priority [%d elements]\n", 1492 logResponse(MemCtrl::READ, (*to_read)->masterId(), 1614 busStateNext = READ; 1682 const Tick col_allowed_at = (busState == READ) [all...] |
/gem5/src/dev/virtio/ |
H A D | fs9p.cc | 107 P9MSG(116, READ),
|
Completed in 19 milliseconds