/gem5/src/mem/cache/tags/ |
H A D | Tags.py | 49 system = Param.System(Parent.any, "System we belong to") 52 size = Param.MemorySize(Parent.size, "capacity in bytes") 55 block_size = Param.Int(Parent.cache_line_size, "block size in bytes") 58 tag_latency = Param.Cycles(Parent.tag_latency, 62 warmup_percentage = Param.Percent(Parent.warmup_percentage, 65 sequential_access = Param.Bool(Parent.sequential_access, 73 entry_size = Param.Int(Parent.cache_line_size, 81 assoc = Param.Int(Parent.assoc, "associativity") 85 Parent.replacement_policy, "Replacement policy") 92 assoc = Param.Int(Parent [all...] |
/gem5/src/dev/alpha/ |
H A D | AlphaBackdoor.py | 38 cpu = Param.BaseCPU(Parent.cpu[0], "Processor") 40 terminal = Param.Terminal(Parent.any, "The console terminal") 41 platform = Param.Platform(Parent.any, "Platform this device is part of.") 42 system = Param.AlphaSystem(Parent.any, "system object")
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/gem5/src/mem/ruby/structures/ |
H A D | ReplacementPolicy.py | 39 block_size = Param.Int(Parent.cache_line_size, "block size in bytes") 41 size = Param.MemorySize(Parent.size, "capacity in bytes") 43 assoc = Param.Int(Parent.assoc, "associativity")
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H A D | WireBuffer.py | 37 ruby_system = Param.RubySystem(Parent.any, "")
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H A D | DirectoryMemory.py | 51 Parent.addr_ranges, "Address range this directory responds to")
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/gem5/src/mem/cache/tags/indexing_policies/ |
H A D | IndexingPolicies.py | 39 size = Param.MemorySize(Parent.size, "capacity in bytes") 42 entry_size = Param.Int(Parent.entry_size, "entry size in bytes") 45 assoc = Param.Int(Parent.assoc, "associativity")
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/gem5/ext/pybind11/tests/ |
H A D | test_call_policies.cpp | 33 // Parent/Child are used in: 46 class Parent { class 48 Parent() { py::print("Allocating parent."); } function in class:Parent 49 ~Parent() { py::print("Releasing parent."); } 54 py::class_<Parent>(m, "Parent") 56 .def(py::init([](Child *) { return new Parent(); }), py::keep_alive<1, 2>()) 57 .def("addChild", &Parent::addChild) 58 .def("addChildKeepAlive", &Parent::addChild, py::keep_alive<1, 2>()) 59 .def("returnChild", &Parent [all...] |
/gem5/src/sim/power/ |
H A D | PowerModel.py | 40 from m5.proxy import Parent 47 # nice features available such as Parent.any 62 subsystem = Param.SubSystem(Parent.any, "subsystem")
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/gem5/src/sim/probe/ |
H A D | Probe.py | 47 manager = Param.SimObject(Parent.any, "ProbeManager")
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/gem5/src/arch/alpha/ |
H A D | AlphaISA.py | 47 system = Param.System(Parent.any, "System this ISA object belongs to")
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/gem5/src/cpu/ |
H A D | IntrControl.py | 35 sys = Param.System(Parent.any, "the system we are part of")
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/gem5/src/dev/storage/ |
H A D | SimpleDisk.py | 37 system = Param.System(Parent.any, "System Pointer")
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/gem5/src/mem/probes/ |
H A D | MemFootprintProbe.py | 47 system = Param.System(Parent.any,
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H A D | StackDistProbe.py | 47 system = Param.System(Parent.any, 51 line_size = Param.Unsigned(Parent.cache_line_size,
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H A D | BaseMemProbe.py | 47 manager = VectorParam.SimObject(Parent.any,
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H A D | MemTraceProbe.py | 56 system = Param.System(Parent.any, "System the probe belongs to")
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/gem5/src/mem/ruby/network/garnet2.0/ |
H A D | GarnetLink.py | 39 link_id = Param.Int(Parent.link_id, "link id") 40 link_latency = Param.Cycles(Parent.latency, "link latency") 41 vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, 43 virt_nets = Param.Int(Parent.number_of_virtual_networks,
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H A D | GarnetNetwork.py | 58 vcs_per_vnet = Param.UInt32(Parent.vcs_per_vnet, 60 virt_nets = Param.UInt32(Parent.number_of_virtual_networks, 62 garnet_deadlock_threshold = Param.UInt32(Parent.garnet_deadlock_threshold, 69 vcs_per_vnet = Param.UInt32(Parent.vcs_per_vnet, 71 virt_nets = Param.UInt32(Parent.number_of_virtual_networks,
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/gem5/src/dev/ps2/ |
H A D | PS2.py | 51 vnc = Param.VncInput(Parent.any, "VNC server providing keyboard input") 61 vnc = Param.VncInput(Parent.any, "VNC server providing mouse input")
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/gem5/src/arch/arm/ |
H A D | ArmTLB.py | 61 sys = Param.System(Parent.any, "system object parameter") 67 sys = Param.System(Parent.any, "system object parameter") 88 sys = Param.System(Parent.any, "system object parameter") 93 tlb = Parent.itb 99 tlb = Parent.dtb
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/gem5/src/dev/serial/ |
H A D | Uart.py | 51 platform = Param.Platform(Parent.any, "Platform this device is part of.") 52 device = Param.SerialDevice(Parent.any, "The terminal")
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/gem5/src/mem/cache/prefetch/ |
H A D | Prefetcher.py | 70 sys = Param.System(Parent.any, "System this prefetcher belongs to") 73 block_size = Param.Int(Parent.cache_line_size, "Block size in bytes") 80 prefetch_on_access = Param.Bool(Parent.prefetch_on_access, 182 SetAssociative(entry_size = 1, assoc = Parent.pt_table_assoc, 183 size = Parent.pt_table_entries), 195 SetAssociative(entry_size = 1, assoc = Parent.ipd_table_assoc, 196 size = Parent.ipd_table_entries), 223 SetAssociative(entry_size = 1, assoc = Parent.signature_table_assoc, 224 size = Parent.signature_table_entries), 238 SetAssociative(entry_size = 1, assoc = Parent [all...] |
/gem5/src/sim/ |
H A D | DVFSHandler.py | 56 sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain,
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/gem5/src/arch/mips/ |
H A D | MipsISA.py | 47 system = Param.System(Parent.any, "System this ISA object belongs to")
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/gem5/src/dev/ |
H A D | Platform.py | 37 intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
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