Searched refs:NAND (Results 1 - 6 of 6) sorted by relevance
| /gem5/ext/mcpat/cacti/ |
| H A D | const.h | 147 #define NAND 2 macro
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| H A D | component.cc | 117 case NAND:
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| H A D | crossbar.cc | 101 g_area += compute_gate_area (NAND, 2, TriS1 * 2 * g_tp.min_w_nmos_,
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| H A D | decoder.cc | 148 compute_gate_area(NAND, 2, w_dec_p[0], w_dec_n[0], area.h);
155 compute_gate_area(NAND, 3, w_dec_p[0], w_dec_n[0], area.h);
527 double tot_area_L1_nand2 = compute_gate_area(NAND, 2, w_L1_nand2_p[0], w_L1_nand2_n[0], g_tp.cell_h_def);
535 tot_area_L1_nand3 = compute_gate_area(NAND, 3, w_L1_nand3_p[0], w_L1_nand3_n[0], g_tp.cell_h_def);
626 cumulative_area_L2 = compute_gate_area(NAND, 2, w_L2_p[0], w_L2_n[0], g_tp.cell_h_def);
630 cumulative_area_L2 = compute_gate_area(NAND, 3, w_L2_p[0], w_L2_n[0], g_tp.cell_h_def);
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| H A D | mat.cc | 724 //TODO: this number should updated using new layout; from the NAND to output NOR should be computed using logical effort
801 /* second stage, from the trasistors in the comparators(both normal row and dummy row) to the NAND gates that combins both half*/
859 //only the dummy row has the extra inverter between NAND and NOR gates
1036 double nand2_area = compute_gate_area(NAND, 2, 0, g_tp.w_comp_n, g_tp.cell_h_def);
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| /gem5/ext/mcpat/ |
| H A D | logic.cc | 264 area.set_area(5 * compute_gate_area(NAND, 2,WdecNANDn,WdecNANDp,
266 + compute_gate_area(NAND, 2,WdecNANDn,WdecNANDn,
276 /* part 1: drain cap of NAND gate */
279 /* part 2: gate cap of NAND gates */
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