Searched refs:MISCREG_TC_STATUS (Results 1 - 3 of 3) sorted by relevance
/gem5/src/arch/mips/ |
H A D | mt.hh | 185 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS), 200 TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS); 216 setRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS), 252 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS), 271 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 273 tc->setMiscReg(MISCREG_TC_STATUS, tcStatus); 286 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 309 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 327 TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS); 334 tc->setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatu [all...] |
H A D | isa.cc | 129 MISCREG_TC_STATUS, MISCREG_TC_BIND, 371 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS); 373 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus); 377 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 379 setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid); 544 TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
|
H A D | registers.hh | 148 MISCREG_TC_STATUS, enumerator in enum:MipsISA::MiscRegIndex
|
Completed in 14 milliseconds