Searched refs:MISCREG_STATUS (Results 1 - 12 of 12) sorted by relevance
/gem5/src/arch/mips/ |
H A D | faults.cc | 106 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 117 tc->setMiscRegNoEffect(MISCREG_STATUS, status); 158 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 160 tc->setMiscReg(MISCREG_STATUS, status);
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H A D | remote_gdb.cc | 177 r.sr = context->readMiscRegNoEffect(MISCREG_STATUS); 194 context->setMiscRegNoEffect(MISCREG_STATUS, r.sr);
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H A D | interrupts.cc | 116 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 137 StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
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H A D | utility.hh | 77 RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
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H A D | mt.hh | 199 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 310 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS); 316 tc->setMiscRegNoEffect(MISCREG_STATUS, status); 328 StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
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H A D | registers.hh | 181 MISCREG_STATUS = 96, //Bank 12: 96-103 enumerator in enum:MipsISA::MiscRegIndex
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H A D | faults.hh | 92 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 283 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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H A D | isa.cc | 128 uint32_t per_tc_regs[] = { MISCREG_STATUS, 327 StatusReg status = readMiscRegNoEffect(MISCREG_STATUS); 339 setMiscRegNoEffect(MISCREG_STATUS, status); 343 setRegMask(MISCREG_STATUS, stat_Mask);
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/gem5/src/arch/riscv/ |
H A D | faults.cc | 61 STATUS status = tc->readMiscReg(MISCREG_STATUS); 127 tc->setMiscReg(MISCREG_STATUS, status); 144 STATUS status = tc->readMiscReg(MISCREG_STATUS); 147 tc->setMiscReg(MISCREG_STATUS, status);
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H A D | interrupts.hh | 78 STATUS status = tc->readMiscReg(MISCREG_STATUS);
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H A D | isa.cc | 69 miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
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H A D | registers.hh | 143 MISCREG_STATUS, enumerator in enum:RiscvISA::MiscRegIndex 439 {CSR_USTATUS, {"ustatus", MISCREG_STATUS}}, 483 {CSR_SSTATUS, {"sstatus", MISCREG_STATUS}}, 500 {CSR_MSTATUS, {"mstatus", MISCREG_STATUS}},
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