Searched refs:MISCREG_ICC_EOIR0_EL1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hh680 MISCREG_ICC_EOIR0_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2399 return MISCREG_ICC_EOIR0_EL1;
4513 InitReg(MISCREG_ICC_EOIR0_EL1)
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc790 case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0

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