Searched refs:MISCREG_ICC_AP1R0_EL1_S (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc1718 apr_misc_reg = MISCREG_ICC_AP1R0_EL1_S;
1825 apr_idx = MISCREG_ICC_AP1R0_EL1_S;
2002 int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
2287 isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S);
/gem5/src/arch/arm/
H A Dmiscregs.hh689 MISCREG_ICC_AP1R0_EL1_S, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc4542 InitReg(MISCREG_ICC_AP1R0_EL1_S)

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