Searched refs:MISCREG_ICC_AP0R0_EL1 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc146 case MISCREG_ICC_AP0R0_EL1: {
768 case MISCREG_ICC_AP0R0_EL1:
1715 apr_misc_reg = MISCREG_ICC_AP0R0_EL1;
1822 apr_idx = MISCREG_ICC_AP0R0_EL1;
2001 int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
2285 uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
/gem5/src/arch/arm/
H A Dmiscregs.hh683 MISCREG_ICC_AP0R0_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc2405 return MISCREG_ICC_AP0R0_EL1;
4523 InitReg(MISCREG_ICC_AP0R0_EL1)

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