Searched refs:IER (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/dev/serial/ |
| H A D | uart8250.cc | 53 if (intrBit & IER) {
80 DPRINTF(Uart, "Scheduling IER interrupt for %s, at cycle %lld\n",
90 : Uart(p, 8), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
119 if (device->dataAvailable() && (IER & UART_IER_RDI))
126 if (!(LCR & 0x80)) { // Intr Enable Register(IER)
127 pkt->setRaw(IER);
195 if (UART_IER_THRI & IER)
202 if (!(LCR & 0x80)) { // Intr Enable Register(IER)
203 IER = pkt->getRaw<uint8_t>();
204 if (UART_IER_THRI & IER)
[all...] |
| H A D | uart8250.hh | 73 uint8_t IER, DLAB, LCR, MCR; member in class:Uart8250
|
| /gem5/src/dev/net/ |
| H A D | ns_gige_reg.h | 47 IER = 0x18, enumerator in enum:DeviceRegisterAddress
|
| H A D | ns_gige.cc | 247 case IER:
543 case IER:
|
Completed in 13 milliseconds