Searched refs:CSR_MHPMEVENT11 (Results 1 - 2 of 2) sorted by relevance

/gem5/src/arch/riscv/
H A Dregisters.hh401 CSR_MHPMEVENT11 = 0x32B, enumerator in enum:RiscvISA::CSRIndex
571 {CSR_MHPMEVENT11, {"mhpmevent11", MISCREG_HPMEVENT11}},
/gem5/tests/test-progs/asmtest/src/riscv/env/
H A Dencoding.h874 #define CSR_MHPMEVENT11 0x32b macro
1366 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)

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