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/gem5/src/systemc/ext/utils/ | ||
H A D | sc_trace_file.hh | diff 13241:9130cd8fe01d Wed Sep 19 19:18:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Fix the default width values for the various sc_trace-s. These were all set to 8 * sizeof(char) instead of using the size of the actual data type being traced. Also add a very simple implementation to the generic sc_signal_in_if<T> sc_trace which just delegates to the sc_trace of the underlying type T. Change-Id: I129df46ef9d49705dc3dac76e30c0a3652c981eb Reviewed-on: https://gem5-review.googlesource.com/c/12818 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/arm/ | ||
H A D | miscregs.hh | diff 9130:8423aa8c2216 Fri Jul 27 16:08:00 EDT 2012 Anthony Gutierrez <atgutier@umich.edu> ARM: fix value of MISCREG_CTR returned by readMiscReg() According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words |
H A D | isa.cc | diff 9130:8423aa8c2216 Fri Jul 27 16:08:00 EDT 2012 Anthony Gutierrez <atgutier@umich.edu> ARM: fix value of MISCREG_CTR returned by readMiscReg() According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words |
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