Searched hist:9050 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/arch/arm/ | ||
| H A D | system.hh | diff 9050:ed4378739b6e Tue Jun 05 01:23:00 EDT 2012 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Fix MPIDR and MIDR register implementation. This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register. |
| H A D | system.cc | diff 9050:ed4378739b6e Tue Jun 05 01:23:00 EDT 2012 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Fix MPIDR and MIDR register implementation. This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register. |
| H A D | ArmSystem.py | diff 9050:ed4378739b6e Tue Jun 05 01:23:00 EDT 2012 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Fix MPIDR and MIDR register implementation. This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register. |
| H A D | isa.cc | diff 9050:ed4378739b6e Tue Jun 05 01:23:00 EDT 2012 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Fix MPIDR and MIDR register implementation. This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register. |
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