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| /gem5/src/mem/ | ||
| H A D | packet.hh | diff 7464:8d92c2737ac8 Wed Jun 16 18:25:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: fix dirty bit setting Only set the dirty bit when we actually write to a block (not if we thought we might but didn't, as in a failed SC or CAS). This requires makeing sure the dirty bit stays set when we get an exclusive (writable) copy in a cache-to-cache transfer from another owner, which n turn requires copying the mem-inhibit flag from timing-mode requests to their associated responses. |
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