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/gem5/src/arch/x86/
H A Dx86_traits.hhdiff 6479:b9ab1b56391b Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
/gem5/src/arch/x86/isa/
H A Doperands.isadiff 6479:b9ab1b56391b Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
/gem5/src/arch/x86/isa/microops/
H A Dregop.isadiff 6479:b9ab1b56391b Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.

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