Searched hist:2646 (Results 1 - 10 of 10) sorted by relevance
| /gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/ | ||
| H A D | config.json | diff 11950:8011fd8ce05c Tue Apr 04 05:24:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the solaris boot stats for new snoopTraffic stat. The following change added the new stat: commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos <david.guillen@arm.com> Date: Thu Jul 21 17:19:14 2016 +0100 mem: Add snoop traffic statistic Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | config.ini | diff 11950:8011fd8ce05c Tue Apr 04 05:24:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the solaris boot stats for new snoopTraffic stat. The following change added the new stat: commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos <david.guillen@arm.com> Date: Thu Jul 21 17:19:14 2016 +0100 mem: Add snoop traffic statistic Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | simout | diff 11950:8011fd8ce05c Tue Apr 04 05:24:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the solaris boot stats for new snoopTraffic stat. The following change added the new stat: commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos <david.guillen@arm.com> Date: Thu Jul 21 17:19:14 2016 +0100 mem: Add snoop traffic statistic Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | stats.txt | diff 11950:8011fd8ce05c Tue Apr 04 05:24:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the solaris boot stats for new snoopTraffic stat. The following change added the new stat: commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos <david.guillen@arm.com> Date: Thu Jul 21 17:19:14 2016 +0100 mem: Add snoop traffic statistic Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/arch/sparc/isa/formats/ | ||
| H A D | integerop.isa | diff 2646:c5f20661d9f3 Fri May 26 18:40:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Implement PR/HPR/ASR for full system Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. |
| H A D | priv.isa | diff 2646:c5f20661d9f3 Fri May 26 18:40:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Implement PR/HPR/ASR for full system Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. |
| /gem5/src/arch/sparc/isa/ | ||
| H A D | operands.isa | diff 2646:c5f20661d9f3 Fri May 26 18:40:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Implement PR/HPR/ASR for full system Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. |
| H A D | decoder.isa | diff 2646:c5f20661d9f3 Fri May 26 18:40:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Implement PR/HPR/ASR for full system Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. |
| /gem5/src/arch/sparc/ | ||
| H A D | process.cc | diff 2646:c5f20661d9f3 Fri May 26 18:40:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Implement PR/HPR/ASR for full system Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. |
| H A D | isa_traits.hh | diff 2646:c5f20661d9f3 Fri May 26 18:40:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Implement PR/HPR/ASR for full system Rip out storage in miscreg file that will never store anything Add storage and defines for Priv and Hyperpriv registers Change defines to match the spec register numbers Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. Use bitfields for things that are rarely used in decoder Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead Still todo: Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs Deal with signaling interrupts on timer expiration Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU Other misc: Instruction decoding needs major help! src/arch/sparc/isa/decoder.isa: Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely changed to bitfields. src/arch/sparc/isa/formats/integerop.isa: These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set at once src/arch/sparc/isa/formats/priv.isa: PrivTick is handled by miscreg now, don't need a seperate class for it src/arch/sparc/isa/operands.isa: prune the number of control regs down to a reasonable amount src/arch/sparc/isa_traits.hh: Replace 8 defines with 1 and flick some bits src/arch/sparc/process.cc: Better to clean the entire registers that specific bits which leads to indetermanistic behavior. src/arch/sparc/regfile.hh: Rip out storage that will never be backed by anything Add storage for Priv and Hyperpriv registers change defines to match the spec change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR. change contextval to an int since both global registers and windowed registers are indexed by int in UA2005. |
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