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| H A D | isa_traits.hh | diff 11961:b6170af6187f Tue Mar 21 00:51:00 EDT 2017 Alec Roelke <ar4jc@virginia.edu> riscv: enable unaligned memory accesses Sometimes an ld instruction will be split across a cache boundary. Previously RISC-V was set to not allow this. This patch fixes that. Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f Reviewed-on: https://gem5-review.googlesource.com/2341 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
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