Searched hist:12945 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/dev/arm/ | ||
| H A D | gic_v2.hh | diff 13109:786adb0cefde Mon Sep 10 19:57:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Fix GICv2 cpu interrupt enable flag Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register as if writing any non-zero value to the register will enable IRQ signaling to the CPU. Instead, only the 2 least significant bits control group0/group1 enablement. This patch is renaming GICC_CTRL underlying data buffer from cpuEnabled to cpuControl and it is making it an array of uint32_t instead of bool. cpuEnabled now becomes a method and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set. Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12945 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | gic_v2.cc | diff 13109:786adb0cefde Mon Sep 10 19:57:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Fix GICv2 cpu interrupt enable flag Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register as if writing any non-zero value to the register will enable IRQ signaling to the CPU. Instead, only the 2 least significant bits control group0/group1 enablement. This patch is renaming GICC_CTRL underlying data buffer from cpuEnabled to cpuControl and it is making it an array of uint32_t instead of bool. cpuEnabled now becomes a method and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set. Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12945 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/systemc/ext/channel/ | ||
| H A D | sc_signal.hh | diff 12945:365bae01b46d Mon Jun 18 22:07:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add m_cur_val and m_new_val to sc_signal. These members are referred to in one of the tests. Change-Id: Iab0110a0e3acf627986664069622704f17b703a1 Reviewed-on: https://gem5-review.googlesource.com/11355 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
Completed in 15 milliseconds