Searched hist:12552 (Results 1 - 3 of 3) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hhdiff 13019:3fa5ab820fa8 Tue Sep 04 06:44:00 EDT 2018 Anouk Van Laer <anouk.vanlaer@arm.com> arch-arm: Correction for address size in EL1&0 translation

When doing EL0/1 translation in stage2, the
physical address size will be defined by the
hypervisor (via VTCR_EL2.ps, not TCR.ips).

See D10.2.121 of the ARM ARM.

Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12552
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
H A Dtable_walker.ccdiff 13019:3fa5ab820fa8 Tue Sep 04 06:44:00 EDT 2018 Anouk Van Laer <anouk.vanlaer@arm.com> arch-arm: Correction for address size in EL1&0 translation

When doing EL0/1 translation in stage2, the
physical address size will be defined by the
hypervisor (via VTCR_EL2.ps, not TCR.ips).

See D10.2.121 of the ARM ARM.

Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12552
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/src/mem/cache/
H A Dcache.ccdiff 12552:5615a3de961f Tue Nov 22 06:38:00 EST 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Populate the secure bit when the temp block is filled

The secure bit should be set when we fill a block with data from a
secure location, as indicated by the packet that triggers the fill.
This patch fixes a bug in which the cache wouldn't populate the secure
bit when filling the temp block.

Change-Id: I95c706146449804ff42b205b25dd79750f3e882a
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8284
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

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