Searched hist:11727 (Results 1 - 3 of 3) sorted by relevance
| /gem5/build_opts/ | ||
| H A D | RISCV | diff 11727:055ae402fbd0 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 5/5] Added missing support for timing CPU models Last of five patches adding RISC-V to GEM5. This patch adds support for timing, minor, and detailed CPU models that was missing in the last four, which basically consists of handling timing-mode memory accesses and telling the minor and detailed models what a no-op instruction should be (addi zero, zero, 0). Patches 1-4 introduced RISC-V and implemented the base instruction set, RV64I, and added the multiply, floating point, and atomic memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] [Fixed some style errors in locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/arch/riscv/ | ||
| H A D | isa_traits.hh | diff 11727:055ae402fbd0 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 5/5] Added missing support for timing CPU models Last of five patches adding RISC-V to GEM5. This patch adds support for timing, minor, and detailed CPU models that was missing in the last four, which basically consists of handling timing-mode memory accesses and telling the minor and detailed models what a no-op instruction should be (addi zero, zero, 0). Patches 1-4 introduced RISC-V and implemented the base instruction set, RV64I, and added the multiply, floating point, and atomic memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] [Fixed some style errors in locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | locked_mem.hh | diff 11727:055ae402fbd0 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 5/5] Added missing support for timing CPU models Last of five patches adding RISC-V to GEM5. This patch adds support for timing, minor, and detailed CPU models that was missing in the last four, which basically consists of handling timing-mode memory accesses and telling the minor and detailed models what a no-op instruction should be (addi zero, zero, 0). Patches 1-4 introduced RISC-V and implemented the base instruction set, RV64I, and added the multiply, floating point, and atomic memory extensions, RV64MAFD. [Fixed compatibility with edit from patch 1.] [Fixed compatibility with hg copy edit from patch 1.] [Fixed some style errors in locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
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