Searched hist:10506 (Results 1 - 7 of 7) sorted by relevance
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | misc.isa | diff 10506:aa23216161fa Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm: Mark some miscregs (timer counter) registers at unverifiable. The checker can't verify timer registers, so it should just grab the version from the executing CPU, otherwise it could get a larger value and diverge execution. |
| H A D | aarch64.isa | diff 10506:aa23216161fa Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm: Mark some miscregs (timer counter) registers at unverifiable. The checker can't verify timer registers, so it should just grab the version from the executing CPU, otherwise it could get a larger value and diverge execution. |
| /gem5/src/arch/arm/ | ||
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