Searched hist:10211 (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | dram_ctrl.hh | diff 10211:e084db2b1527 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Merge DRAM latency calculation and bank state update This patch merges the two control paths used to estimate the latency and update the bank state. As a result of this merging the computation is now in one place only, and should be easier to follow as it is all done in absolute (rather than relative) time. As part of this change, the scheduling is also refined to ensure that we look at a sensible estimate of the bank ready time in choosing the next request. The bank latency stat is removed as it ends up being misleading when the DRAM access code gets evaluated ahead of time (due to the eagerness of waking the model up for scheduling the next request). |
| H A D | dram_ctrl.cc | diff 10211:e084db2b1527 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Merge DRAM latency calculation and bank state update This patch merges the two control paths used to estimate the latency and update the bank state. As a result of this merging the computation is now in one place only, and should be easier to follow as it is all done in absolute (rather than relative) time. As part of this change, the scheduling is also refined to ensure that we look at a sensible estimate of the bank ready time in choosing the next request. The bank latency stat is removed as it ends up being misleading when the DRAM access code gets evaluated ahead of time (due to the eagerness of waking the model up for scheduling the next request). |
Completed in 18 milliseconds