| /gem5/src/systemc/ext/tlm_utils/ |
| H A D | convenience_socket_bases.h | 76 explicit convenience_socket_cb_holder(convenience_socket_base *owner) : argument
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| H A D | multi_socket_bases.h | 179 callback_binder_fw(multi_socket_base *owner, int id) : argument
299 callback_binder_bw(multi_socket_base *owner, int id) : argument
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| H A D | passthrough_target_socket.h | 104 explicit process(passthrough_socket_base *owner) : argument
333 process(passthrough_socket_base *owner) : argument
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| H A D | simple_initiator_socket.h | 87 explicit process(simple_socket_base *owner) : argument
238 explicit process(simple_socket_base *owner) : argument
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| /gem5/src/mem/ |
| H A D | external_master.hh | 74 ExternalMaster &owner; member in class:ExternalMaster::ExternalPort
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| H A D | external_slave.hh | 74 ExternalSlave &owner; member in class:ExternalSlave::ExternalPort
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| H A D | qport.hh | 79 QueuedSlavePort(const std::string& name, SimObject* owner, argument
132 QueuedMasterPort(const std::string& name, SimObject* owner, argument
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| H A D | port.hh | 84 SimObject &owner; member in class:MasterPort
268 SimObject& owner; member in class:SlavePort
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| H A D | external_slave.cc | 86 getExternalPort( const std::string &name_, ExternalSlave &owner, const std::string &port_data) argument
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| /gem5/src/learning_gem5/part2/ |
| H A D | simple_memobj.hh | 57 SimpleMemobj *owner; member in class:SimpleMemobj::CPUSidePort
69 CPUSidePort(const std::string& name, SimpleMemobj *owner) : argument
139 SimpleMemobj *owner; member in class:SimpleMemobj::MemSidePort
148 MemSidePort(const std::string& name, SimpleMemobj *owner) argument
[all...] |
| H A D | simple_cache.hh | 63 SimpleCache *owner; member in class:SimpleCache::CPUSidePort
75 CPUSidePort(const std::string& name, int id, SimpleCache *owner) : argument
146 SimpleCache *owner; member in class:SimpleCache::MemSidePort
155 MemSidePort(const std::string& name, SimpleCache *owner) argument
[all...] |
| /gem5/src/dev/ |
| H A D | intpin.hh | 114 IntSourcePin(const std::string &_name, PortID _id, Device *owner, argument
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| /gem5/util/tlm/src/ |
| H A D | sc_slave_port.cc | 388 getExternalPort(const std::string &name, ExternalSlave &owner, const std::string &port_data) argument
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| H A D | sc_master_port.cc | 416 getExternalPort(const std::string &name, ExternalMaster &owner, const std::string &port_data) argument
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| /gem5/ext/sst/ |
| H A D | gem5.cc | 252 getExternalPort(const std::string &name, ExternalMaster &owner, const std::string &port_data) argument
262 getExternalPort(const std::string &name, ExternalSlave &owner, const std::string &port_data) argument
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| /gem5/src/mem/cache/prefetch/ |
| H A D | queued.hh | 59 QueuedPrefetcher *owner; member in struct:QueuedPrefetcher::DeferredPacket
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| /gem5/src/mem/ruby/profiler/ |
| H A D | AddressProfiler.cc | 248 profileGetX(Addr datablock, Addr PC, const Set& owner, const Set& sharers, NodeID requestor) argument
266 profileGetS(Addr datablock, Addr PC, const Set& owner, const Set& sharers, NodeID requestor) argument
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| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.hh | 262 TraceCPU* owner; member in class:TraceCPU::IcachePort
319 TraceCPU* owner; member in class:TraceCPU::DcachePort
505 TraceCPU& owner; member in class:TraceCPU::FixedRetryGen
991 TraceCPU& owner; member in class:TraceCPU::ElasticDataGen
[all...] |
| /gem5/src/sim/ |
| H A D | syscall_emul.hh | 1567 Process *owner = ctc->getProcessPtr(); local
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| H A D | syscall_emul.cc | 723 uint32_t owner = p->getSyscallArg(tc, index); local
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