Searched defs:CSR_MIP (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/arch/riscv/ | ||
| H A D | registers.hh | 340 CSR_MIP = 0x344, enumerator in enum:RiscvISA::CSRIndex |
| /gem5/tests/test-progs/asmtest/src/riscv/env/ | ||
| H A D | encoding.h | 807 #define CSR_MIP 0x344 macro |
Completed in 10 milliseconds