Searched refs:writeback (Results 1 - 10 of 10) sorted by relevance

/gem5/src/dev/net/
H A Di8254xGBe.hh95 rxDescCache.writeback(0);
105 rxDescCache.writeback(0);
115 txDescCache.writeback(0);
125 txDescCache.writeback(0);
255 // What the alignment is of the next descriptor writeback
280 void writeback(Addr aMask);
296 /** Called by event when dma to writeback descriptors is completed
490 "Completion writeback Addr: %#x enabled: %d\n",
499 DPRINTF(EthernetDesc, "Completion writeback complete\n");
H A Di8254xGBe.cc275 rxDescCache.writeback(0);
857 IGbE::DescCache<T>::writeback(Addr aMask) function in class:IGbE::DescCache
862 // Check if this writeback is less restrictive that the previous
1094 writeback(wbAlignment);
1953 writeback(0);
1958 writeback((igbe->cacheBlockSize()-1)>>4);
1962 writeback((igbe->cacheBlockSize()-1)>>4);
2156 txDescCache.writeback((cacheBlockSize()-1)>>4);
2175 txDescCache.writeback(0);
2180 "writeback stoppin
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ud/
H A Dstructural.S8 # writeback port (e.g. fadd followed by fsgnj)
/gem5/src/dev/storage/
H A Ddisk_image.hh134 void writeback();
H A Ddisk_image.cc377 CowDiskImage::writeback() function in class:CowDiskImage
/gem5/src/arch/arm/insts/
H A Dmacromem.cc58 bool index, bool up, bool user, bool writeback,
71 bool pc_temp = load && writeback && bits(reglist, 15);
79 + (writeback? 1 : 0)
82 numMicroops = ones + (writeback ? 1 : 0);
130 if (!writeback && reg_idx2 == INTREG_PC) {
131 // No writeback if idx==pc, set appropriate flags
153 if (writeback && reg_idx == INTREG_PC) {
155 // writeback, ensure the pc load/branch is the last uop.
170 if (!writeback && reg_idx == INTREG_PC) {
192 if (writeback
56 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, bool index, bool up, bool user, bool writeback, bool load, uint32_t reglist) argument
250 bool writeback = (mode != AddrMd_Offset); local
1437 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, RegIndex vd, bool single, bool up, bool writeback, bool load, uint32_t offset) argument
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H A Dmacromem.hh434 bool writeback, bool load, uint32_t reglist);
540 bool writeback, bool load, uint32_t offset);
/gem5/src/cpu/o3/
H A Dlsq_unit_impl.hh79 lsqPtr->writeback(inst, pkt);
90 return "Store writeback";
127 // Only loads, store conditionals and atomics perform the writeback
131 writeback(inst, state->request()->mainPacket());
641 // writeback if we haven't had a fault by here.
777 /* Only store conditionals and atomics need a writeback. */
949 LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt) function in class:LSQUnit
H A Dlsq_unit.hh71 * committing, while store entries are freed once they writeback. The
159 /** Whether or not the store can writeback. */
333 /** Returns if there are any stores to writeback. */
336 /** Returns the number of stores to writeback. */
339 /** Returns if the LSQ unit will writeback on this cycle. */
359 void writeback(const DynInstPtr &inst, PacketPtr pkt);
440 /** Constructs a writeback event. */
444 /** Processes the writeback event. */
493 /** The number of store instructions in the SQ waiting to writeback. */
807 // Do not generate a writeback even
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/gem5/src/arch/arm/
H A Dtypes.hh136 Bitfield<21> writeback; member in namespace:ArmISA

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