Searched refs:tWTR (Results 1 - 2 of 2) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | DRAMCtrl.py | 207 tWTR = Param.Latency("Write to read, same rank switching time") variable in class:DRAMCtrl 372 tWTR = '7.5ns' variable in class:DDR3_1600_8x8 609 tWTR = '5ns' variable in class:DDR4_2400_16x4 780 # Irrespective of speed grade, tWTR is 7.5 ns 781 tWTR = '7.5ns' variable in class:LPDDR2_S4_1066_1x32 869 tWTR = '15ns' variable in class:WideIO_200_1x128 948 # Irrespective of speed grade, tWTR is 7.5 ns 949 tWTR = '7.5ns' variable in class:LPDDR3_1600_1x32 1059 tWTR = '5ns' variable in class:GDDR5_4000_2x32 1133 tWTR variable in class:HBM_1000_4H_1x128 [all...] |
| H A D | dram_ctrl.cc | 92 wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST), |
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