Searched refs:tRTW (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | DRAMCtrl.py | 210 tRTW = Param.Latency("Read to write, same rank switching time") variable in class:DRAMCtrl 378 tRTW = '2.5ns' variable in class:DDR3_1600_8x8 615 tRTW = '1.666ns' variable in class:DDR4_2400_16x4 784 tRTW = '3.75ns' variable in class:LPDDR2_S4_1066_1x32 872 tRTW = '10ns' variable in class:WideIO_200_1x128 952 tRTW = '2.5ns' variable in class:LPDDR3_1600_1x32 1065 tRTW = '2ns' variable in class:GDDR5_4000_2x32 1137 tRTW = '4ns' variable in class:HBM_1000_4H_1x128 |
| H A D | dram_ctrl.hh | 988 const Tick tRTW; member in class:DRAMCtrl |
| H A D | dram_ctrl.cc | 86 tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 92 wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST), 1543 switched_cmd_type ? std::min(tRTW, tCS) : 0); |
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