Searched refs:tRCD (Results 1 - 4 of 4) sorted by relevance
/gem5/src/mem/ |
H A D | DRAMCtrl.py | 158 tRCD = Param.Latency("RAS to CAS delay") variable in class:DRAMCtrl 360 tRCD = '13.75ns' variable in class:DDR3_1600_8x8 458 tRCD = '10.2ns' variable in class:HMC_2500_1x32 516 tRCD = '13.09ns' variable in class:DDR3_2133_8x8 589 tRCD = '14.16ns' variable in class:DDR4_2400_16x4 751 tRCD = '15ns' variable in class:LPDDR2_S4_1066_1x32 850 tRCD = '18ns' variable in class:WideIO_200_1x128 918 tRCD = '18ns' variable in class:LPDDR3_1600_1x32 1031 tRCD = '12ns' variable in class:GDDR5_4000_2x32 1033 # tCL is not directly found in datasheet and assumed equal tRCD 1115 tRCD = '15ns' variable in class:HBM_1000_4H_1x128 [all...] |
H A D | drampower.cc | 81 timingSpec.RCD = divCeil(p->tRCD, p->tCK);
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H A D | dram_ctrl.cc | 88 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 260 nextBurstAt = curTick() + tRP + tRCD; 279 latency = tRP + tRCD + tCL; 988 bank_ref.rdAllowedAt = std::max(act_tick + tRCD, bank_ref.rdAllowedAt); 989 bank_ref.wrAllowedAt = std::max(act_tick + tRCD, bank_ref.wrAllowedAt); 1145 // respect any constraints on the command (e.g. tRCD or tCCD) 1301 nextReqTime = nextBurstAt - (tRP + tRCD); 1646 const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick()); 1685 Tick col_at = std::max(col_allowed_at, act_at + tRCD); [all...] |
H A D | dram_ctrl.hh | 993 const Tick tRCD; member in class:DRAMCtrl 1050 * and access, it is tRP + tRCD + tCL.
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