Searched refs:tCS (Results 1 - 3 of 3) sorted by relevance

/gem5/src/mem/
H A DDRAMCtrl.py216 tCS = Param.Latency("Rank to rank switching time") variable in class:DRAMCtrl
381 tCS = '2.5ns' variable in class:DDR3_1600_8x8
479 tCS = '0.8ns' variable in class:HMC_2500_1x32
618 tCS = '1.666ns' variable in class:DDR4_2400_16x4
787 tCS = '3.75ns' variable in class:LPDDR2_S4_1066_1x32
875 tCS = '10ns' variable in class:WideIO_200_1x128
955 tCS = '2.5ns' variable in class:LPDDR3_1600_1x32
1140 tCS = '0ns' variable in class:HBM_1000_4H_1x128
1194 tCS = '2ns' variable in class:HBM_1000_4H_1x64
H A Ddram_ctrl.hh989 const Tick tCS; member in class:DRAMCtrl
H A Ddram_ctrl.cc86 tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST),
91 activationLimit(p->activation_limit), rankToRankDly(tCS + tBURST),
1164 // tBURST; Add tCS for different ranks
1186 // Need to account for rank-to-rank switching with tCS
1459 // bus turnaround delay which will be tCS (different rank) case
1460 to_read = chooseNext((*queue), switched_cmd_type ? tCS : 0);
1543 switched_cmd_type ? std::min(tRTW, tCS) : 0);

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