Searched refs:tCL (Results 1 - 4 of 4) sorted by relevance

/gem5/src/mem/
H A DDRAMCtrl.py161 tCL = Param.Latency("CAS latency") variable in class:DRAMCtrl
361 tCL = '13.75ns' variable in class:DDR3_1600_8x8
459 tCL = '9.9ns' variable in class:HMC_2500_1x32
517 tCL = '13.09ns' variable in class:DDR3_2133_8x8
590 tCL = '14.16ns' variable in class:DDR4_2400_16x4
754 tCL = '15ns' variable in class:LPDDR2_S4_1066_1x32
851 tCL = '18ns' variable in class:WideIO_200_1x128
921 tCL = '15ns' variable in class:LPDDR3_1600_1x32
1033 # tCL is not directly found in datasheet and assumed equal tRCD
1034 tCL variable in class:GDDR5_4000_2x32
1116 tCL = '15ns' variable in class:HBM_1000_4H_1x128
[all...]
H A Ddrampower.cc82 timingSpec.RL = divCeil(p->tCL, p->tCK);
H A Ddram_ctrl.hh994 const Tick tCL; member in class:DRAMCtrl
1050 * and access, it is tRP + tRCD + tCL.
H A Ddram_ctrl.cc88 tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS),
92 wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST),
279 latency = tRP + tRCD + tCL;
1154 dram_pkt->readyTime = cmd_at + tCL + tBURST;

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