/gem5/src/systemc/tests/systemc/misc/user_guide/chpt3.2/ |
H A D | fsmr.cpp | 45 int state = 0; local 53 switch(state) { 55 if (c == pattern[0]) state = 1; 56 else state = 0; 60 if (c == pattern[1]) state = 2; 61 else state = 0; 65 if (c == pattern[2]) state = 3; 66 else state = 0; 72 state = 0; 75 cout << "Error: FSM in bad state [all...] |
/gem5/src/systemc/tests/systemc/misc/user_guide/chpt3.1/ |
H A D | fsmr.cpp | 45 int state = 0; local 53 switch(state) { 55 if (c == pattern[0]) state = 1; 56 else state = 0; 60 if (c == pattern[1]) state = 2; 61 else state = 0; 65 if (c == pattern[2]) state = 3; 66 else state = 0; 72 state = 0; 75 cout << "Error: FSM in bad state [all...] |
/gem5/src/mem/ruby/network/garnet2.0/ |
H A D | OutVcState.hh | 51 isInState(VC_state_type state, Cycles request_time) argument 53 return ((m_vc_state == state) && (request_time >= m_time) ); 56 setState(VC_state_type state, Cycles time) argument 58 m_vc_state = state;
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/gem5/src/base/ |
H A D | random.cc | 78 // get the state from the generator 81 std::string state = oss.str(); local 82 paramOut(cp, "mt_state", state); 90 // the random generator state did not use to be part of the 91 // checkpoint state, so be forgiving in the unserialization and 93 std::string state; local 94 if (optParamIn(cp, "mt_state", state)) { 95 std::istringstream iss(state);
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/gem5/ext/testlib/ |
H A D | __init__.py | 30 from .state import *
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/gem5/src/mem/slicc/generate/ |
H A D | tex.py | 48 for state in sm.states: 49 state_str = state.short 52 trans = sm.get_transition(state, event) 56 if trans.getNextStateShorthand() != state.short:
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/gem5/ext/pybind11/include/pybind11/ |
H A D | options.h | 31 // Setter methods (affect the global state): 41 // Getter methods (return the global state): 52 struct state { struct in class:options 57 static state &global_state() { 58 static state instance; 62 state previous_state;
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/gem5/src/dev/arm/ |
H A D | EnergyCtrl.py | 51 def generateDeviceTree(self, state): 52 node = self.generateBasicPioDeviceNode(state, 'gem5_energy_ctrl',
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H A D | VirtIOMMIO.py | 57 def generateDeviceTree(self, state): 58 node = self.generateBasicPioDeviceNode(state, 'virtio', self.pio_addr,
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H A D | Gic.py | 150 def generateDeviceTree(self, state): 161 state.addrCells(gic.dist_addr) + 162 state.sizeCells(0x1000) + 163 state.addrCells(gic.cpu_addr) + 164 state.sizeCells(0x1000) + 165 state.addrCells(self.hv_addr) + 166 state.sizeCells(0x2000) + 167 state.addrCells(self.vcpu_addr) + 168 state.sizeCells(0x2000) ) 190 def generateDeviceTree(self, state) [all...] |
/gem5/src/systemc/tests/systemc/misc/sim_tests/multtrans/multtrans0/ |
H A D | multtrans0.cpp | 84 int state; local 96 state = 0; 105 switch(state) { 106 case 0: // initial state 107 cout << "In state 0 :: " << flush; 111 cout << "staying in state 0" << endl; 114 state = 1; 115 cout << "going to state 1" << endl; 120 state = 2; 121 cout << "going to state [all...] |
/gem5/util/plot_dram/ |
H A D | PlotPowerStates.py | 158 #### state time values #### 165 # Now grab the state, i.e. 'ACT' 166 state = statistic.split('::')[1] 168 results[delay][bank_util][seq_bytes][state] = \ 170 #### state energy values #### 176 state = StatToKey[statistic] 178 results[delay][bank_util][seq_bytes][state] = senergy 187 # Now grab the state energy, .e.g 'ACT' 188 state = statistic.split('::')[1] 189 idleResults[state] [all...] |
/gem5/src/cpu/ |
H A D | translation.hh | 52 * This class captures the state of an address translation. A translation 59 * translation state which deal with the possible split correctly. 78 * Single translation state. We set the number of outstanding 91 * Split translation state. We copy all state into this class, set the 121 // For ease later, we copy some state to the main request. 209 * This class represents part of a data address translation. All state for 212 * index variable determines this but is simply passed on to the state class. 214 * translation state class indicate that the whole translation is complete 222 WholeTranslationState *state; member in class:DataTranslation [all...] |
/gem5/src/mem/slicc/ast/ |
H A D | TransitionDeclAST.py | 62 for state in self.states: 63 if state not in machine.states: 64 self.error("Invalid state: %s is not part of machine: %s" % \ 65 (state, machine)) 66 next_state = self.next_state or state 71 t = Transition(self.symtab, machine, state, event, next_state,
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/gem5/src/arch/arm/ |
H A D | nativetrace.hh | 77 uint64_t state[2][STATE_NUMVALS]; member in struct:Trace::ArmNativeTrace::ThreadState 88 state[0][i] = state[1][i] = 0; 90 newState = state[0]; 91 oldState = state[1];
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H A D | ArmSystem.py | 101 def generateDeviceTree(self, state): 112 state.addrCells(mem_range.start) + 113 state.sizeCells(mem_range.size()) )) 117 root.append(state.addrCellsProperty()) 118 root.append(state.sizeCellsProperty()) 124 for node in self.recurseDeviceTree(state): 157 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1) 158 rootNode = self.generateDeviceTree(state)
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/gem5/src/mem/slicc/symbols/ |
H A D | Transition.py | 32 def __init__(self, table, machine, state, event, nextState, actions, 34 ident = "%s|%s" % (state, event) 37 self.state = machine.states[state] 65 (self.state, self.event, self.nextState, self.actions)
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/gem5/src/systemc/tests/systemc/kernel/process_control/test01/ |
H A D | test01.cpp | 69 static int state = 0; local 70 switch ( state ) 76 << "," << state << ") initialization call " << endl; 81 << "," << state << ") after wait on m_clk.posedge_event() " 87 << "," << state << ") after wait on m_clk.posedge_event() " 93 << "," << state << ") after wait on m_clk.negedge() " << endl; 98 << "," << state << ") after wait on m_event1 & m_event2 " 104 << "," << state << ") after wait on m_clk.posedge_event() " 108 state = state [all...] |
/gem5/src/systemc/tests/systemc/misc/parsing/T_1_1_2_4/ |
H A D | T_1_1_2_4.cpp | 47 int state; local
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/gem5/src/systemc/tests/systemc/misc/parsing/T_1_1_2_5/ |
H A D | T_1_1_2_5.cpp | 47 int state; local
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/gem5/src/dev/ |
H A D | Platform.py | 40 def annotateCpuDeviceNode(self, cpu, state):
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H A D | Device.py | 55 def generateBasicPioDeviceNode(self, state, name, pio_addr, 59 state.addrCells(pio_addr) + 60 state.sizeCells(size) )) 96 def addIommuProperty(self, state, node): 106 [ state.phandle(self._iommu), self.sid ]))
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/gem5/src/cpu/minor/ |
H A D | fetch1.hh | 86 * issuing an ITLB lookup (state becomes InTranslation) with a 90 * Translated packets (state becomes Translation) are then passed to the 91 * memory system and the transfers queue (state becomes RequestIssuing). 93 * changing the state to IcacheNeedsRetry). 95 * Responses from the memory system alter the request object (state 121 FetchRequestState state; member in class:Minor::Fetch1::FetchRequest 154 bool isComplete() const { return state == Complete; } 173 state(NotIssued), 223 /** Cycle-by-cycle state */ 229 to FetchWaitingForPC. The PC is not valid in this state */ 258 FetchState state; member in struct:Minor::Fetch1::Fetch1ThreadInfo [all...] |
/gem5/tests/testing/ |
H A D | results.py | 78 def __init__(self, name, state, message="", stderr="", stdout="", 81 self.state = state 88 return self.state == UnitResult.STATE_SKIPPED 91 return self.state == UnitResult.STATE_OK 94 return UnitResult.state_names[self.state] 236 if test.state == UnitResult.STATE_OK: 238 elif test.state == UnitResult.STATE_SKIPPED: 240 elif test.state == UnitResult.STATE_FAILURE: 242 elif test.state [all...] |
/gem5/src/dev/i2c/ |
H A D | bus.cc | 56 : BasicPioDevice(p, 0x1000), scl(1), sda(1), state(IDLE), currBit(7), 67 * Reads will always be to SB_CONTROLS. The kernel wants to know the state 99 state = RECEIVING_ADDR; 114 state = IDLE; 118 // Only change state when the clock is transitioning from low to high. 122 switch (state) { 131 state = SENDING_DATA; 134 state = RECEIVING_DATA; 164 panic("Invalid state on posedge of clock in I2CBus::write.\n"); 221 SERIALIZE_ENUM(state); [all...] |