Searched refs:shareable (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/
H A Dpagetable.hh142 bool shareable; member in struct:ArmISA::TlbEntry
158 shareable(false), outerShareable(false), xn(0), pxn(0)
173 shareable(false), outerShareable(false), xn(0), pxn(0)
246 shareable ? 0x3 : 0) << 7);
265 ((shareable ? 1:0) << 7) |
314 SERIALIZE_SCALAR(shareable); variable
344 UNSERIALIZE_SCALAR(shareable); variable
H A Dstage2_lookup.cc153 stage1Te.shareable |= stage2Te->shareable;
157 // something Non-cacheable at each level is outer shareable
158 stage1Te.shareable = true;
162 stage1Te.shareable = true;
H A Dtable_walker.cc1030 te.shareable = false; // default value
1038 te.shareable = true;
1045 te.shareable = true;
1051 te.shareable = s;
1057 te.shareable = s;
1064 te.shareable = s;
1076 te.shareable = s;
1080 case 8: // Non-shareable Device
1083 te.shareable = false;
1092 te.shareable
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H A Dtable_walker.hh89 virtual bool shareable() const function in class:ArmISA::TableWalker::DescriptorBase
91 panic("shareable() not implemented for this class\n");
208 /** If the section is shareable. See texcb() comment. */
209 bool shareable() const function in class:ArmISA::TableWalker::L1Descriptor
346 /** If the section is shareable. See texcb() comment. */
347 bool shareable() const function in class:ArmISA::TableWalker::L2Descriptor
H A Dtlb.cc1117 temp_te.shareable = true;
1123 temp_te.shareable = false;
1127 DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: "
1129 temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs,
1152 "Setting memory attributes: shareable: %d, innerAttrs: %d, "
1154 te->shareable, te->innerAttrs, te->outerAttrs,

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