Searched refs:rn (Results 1 - 7 of 7) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dmacromem.cc57 OpClass __opClass, IntRegIndex rn,
68 bool copy_base = (bits(reglist, rn) && load) || !ones;
100 *uop++ = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
128 copy_base ? INTREG_UREG0 : rn, up, addr);
158 copy_base ? INTREG_UREG0 : rn, up, addr);
162 copy_base ? INTREG_UREG0 : rn, up, addr);
166 copy_base ? INTREG_UREG0 : rn, up, addr);
180 *uop = new MicroStrUop(machInst, reg_idx, rn, up, addr);
195 *uop++ = new MicroAddiUop(machInst, rn, rn, one
56 MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, bool index, bool up, bool user, bool writeback, bool load, uint32_t reglist) argument
242 PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, bool exclusive, bool acrel, int64_t imm, AddrMode mode, IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) argument
459 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm) argument
554 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument
822 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm) argument
917 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument
1120 VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb) argument
1205 VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb) argument
1290 VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate) argument
1364 VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate) argument
1437 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, RegIndex vd, bool single, bool up, bool writeback, bool load, uint32_t offset) argument
[all...]
H A Dpred_inst.cc56 (IntRegIndex)(uint32_t)machInst.rn,
70 (IntRegIndex)(uint32_t)machInst.rn,
H A Dmacromem.hh208 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
220 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
232 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
244 RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize,
433 IntRegIndex rn, bool index, bool up, bool user,
453 IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
499 unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
507 bool all, unsigned elems, RegIndex rn, RegIndex vd,
519 unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
527 bool all, unsigned elems, RegIndex rn, RegInde
[all...]
H A Dstatic_inst.cc590 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
604 if (rn != INTREG_ZERO) {
608 printIntReg(os, rn);
H A Dstatic_inst.hh189 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
/gem5/src/arch/power/
H A Dmiscregs.hh95 Bitfield<2,1> rn; member in namespace:PowerISA
/gem5/src/arch/arm/
H A Dtypes.hh123 Bitfield<19, 16> rn; member in namespace:ArmISA

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